Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-5
8.4 External Signal Description
The following sections provide an overview and detailed descriptions of the IPIC signals.
8.4.1 Overview
The device has 4 distinct external interrupt request input signals (IRQ0, IRQ1, IRQ2 and IRQ3). The IPIC
interface signals are listed in Table 8-1.
8.4.2 Detailed Signal Descriptions
Table 8-2 provides detailed descriptions of the external IPIC signals.
Table 8-1. IPIC Signal Properties
Name Port Function I/O Reset Requires Pull Up
INTA INTA Interrupt request output O Z Yes
IRQ0, IRQ1,
IRQ2, IRQ3
IRQ0, IRQ1,
IRQ2, IRQ3
External interrupts I — Yes
MCP_OUT MCP_OUT Interrupt request output O Z Yes
Table 8-2. IPIC External Signals—Detailed Signal Descriptions
Signal I/O Description
INTA
OD Interrupt request out. Active-low, open drain. When the IPIC is programmed in core disable mode, this output
reflects the raw interrupts generated by on-chip sources. See Section 8.3, “Modes of Operation” for details.
State
Meaning
Asserted—At least one interrupt is currently being signalled to the external system.
Negated—Indicates no interrupt sources currently routed to INTA.
Timing Because external interrupts are asynchronous with respect to the external clock, both assertion
and negation of INTA
occur asynchronously with respect to the interrupt source. All timing
given here is approximate.
Assertion—Intrernal interrupt source: 3 system bus clock cycles after the interrupt occurs.
External interrupt source: 4 cycles after the interrupt occurs.
Negation—Follows interrupt source negation with the following delay:
Internal interrupt: 3 system bus clock cycles. External interrupt: 4 cycles.
IRQ
0, IRQ1,
IRQ
2, IRQ3
I Interrupt request 0, 1, 2, and 3. The sense (level or edge) of each of these signals is programmable. All of
these inputs can be driven completely asynchronously.
State
Meaning
Asserted—When an external interrupt request signal is asserted the priority is checked by the
IPIC unit, and the interrupt is conditionally passed to the processor.
Negated—There is no incoming interrupt from that source.
Timing Assertion—All of these inputs can be asserted completely asynchronously.
Negation—Interrupts programmed as level-sensitive must remain asserted until serviced.