Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-4 Freescale Semiconductor
• External and internal non-maskable machine check conditions, signaled by the sources listed in
Table 8-23 through mcp
The interrupt controller provides the ability to mask each interrupt source. Any source that can be caused
by multiple events are also maskable.
When the IPIC receives an internal or external interrupt, its configuration register is checked to determine
if it should be serviced as a normal external interrupt by the processor core (through the int signal) or if
the incoming interrupt has been configured as a critical or system management interrupt, the IPIC
completes the processing of the interrupt by asserting cint or smi to the core. The assertion of the cint or
smi signal to the core causes the interrupt to be serviced as a critical or a system management interrupt,
respectively.
8.2 Features
The IPIC unit implements the following features:
• Support for external and internal discrete vectorized interrupt sources
• Support for external and internal non-maskable machine check conditions, signaled by mcp
• Programmable highest priority request (can be programmed to support a critical (cint) or system
management interrupt (smi) type)
• Two programmable priority mixed groups of four on-chip and four external interrupt signals with
two priority schemes for each group: grouped and spread
• Four programmable priority internal groups of eight on-chip interrupt signals with two priority
schemes for each group: grouped and spread
• Two highest priority interrupts from each group can be programmed to support a critical or system
management interrupt type
• External and internal interrupts directed to host processor
• Unique vector number for each interrupt source
8.3 Modes of Operation
The IPIC unit can operate in the core enable or core disable mode.
8.3.1 Core Enable Mode
In core enable mode, all internal interrupts are routed to and from the IPIC; the interrupts are sent to the
e300 core. In this mode all machine check interrupts are gathered by the IPIC unit and sent to the e300 core.
8.3.2 Core Disable Mode
MPC8308 supports core disable mode only for debug purposes. The e300 core may be put in Core Disable
mode by RCW. In this mode, JTAG will have access to the registers for reads and writes.