Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-2 Freescale Semiconductor
critical interrupt exception. The smi signal is the system management interrupt output from the IPIC to the
processor core and causes the system management interrupt exception. The machine check exception is
caused by the internal mcp signal generated by the IPIC, informing the host processor of error conditions,
assertion of the external IRQ0 machine-check request (enabled when SEMSR[SIRQ0] = 1), and other
conditions.
Table 8-1 shows the relationship of the various functional blocks and external signals of the device to the
IPIC unit.
The IPIC receives interrupt request signals from the following two sources:
• External to the integrated device
• Internal to the integrated device
The unit selects the highest priority interrupt from all current interrupts and forwards it to the internal
processor core, or off-chip for external servicing.
The IPIC also manages an internal non-maskable machine-check processor (mcp) signal and the interrupt
generated by the off-chip interrupt sources (IRQ0, IRQ1, IRQ2, and IRQ3).
The interrupt router of the IPIC monitors the outputs of the internal configuration registers. When the
priority is highest in one of the received interrupt signals, the IPIC sets the corresponding bit in one of the
following registers:
• System internal interrupt pending register (SIPNR)
• System external interrupt pending register (SEPNR)
If the interrupt is not masked, the IPIC asserts the int signal to indicate an interrupt request to the processor.
When the processor is running the specific int, cint, or smi interrupt handler code, the processor must
vectorize the external interrupt handler by explicitly (in software) reading the corresponding interrupt
vector register (SIVCR, SCVCR or SMVCR). In response to this read, the IPIC unit returns the vector
(associated with the interrupt source) to the interrupt handler routine. In addition, the handler can vectorize
different branches of interrupt handling.