Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-1
Chapter 8
Integrated Programmable Interrupt Controller (IPIC)
This chapter describes the integrated programmable interrupt controller (IPIC), including a definition of
the external signals and their functions. Also, the configuration, control, and status registers are described
in this chapter. Note that individual chapters in this reference manual describe specific initialization
aspects for each individual block.
8.1 Introduction
This chapter describes the IPIC interrupt protocol, various types of interrupt sources controlled by the IPIC
unit, and the IPIC registers with some programming guidelines. The interrupt controller provides interrupt
management that is responsible for receiving hardware-generated interrupts from different sources (both
internal and external). It also prioritizes and delivers the interrupts to the CPU for servicing. The IPIC
prioritizes and manages interrupts from the following controller units:
• DDR memory controller (DDR2)
• Enhanced local bus memory controller (eLBC)
• DMA controller (DMA)
• Dual three-speed Ethernet controllers (eTSEC1 and eTSEC2) with IEEE 1588 support
• DUART communication module (DUART)
• USB 2.0 dual role controller (USB DR)
• System bus arbiter (SBA)
• Periodic interval timer (PIT)
• Real time clock timer (RTC ALR and RTC SEC)
• Global timer (GTM1) with 4 instances as GTM1_1, GTM1_2, GTM1_3, and GTM1_4
• Software watchdog timer (WDT)
•Two I
2
C controller (I
2
C1 and I
2
C2)
• SPI controller (SPI)
• General-purpose I/O controller (GPIO)
• External pins (IRQ0, IRQ1, IRQ2, and IRQ3)
• PCI Express controller
• Enhanced secure digital host controller (eSDHC)
• Message shared interrupt (MSI)
The interrupt sources controlled by the IPIC unit cause exceptions in the processor core. The internal
interrupt (int) signal is the main interrupt output from the IPIC to the core and it causes the regular interrupt
exception. The cint signal is the critical interrupt output from the IPIC to the processor core and causes the