Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xxvii
Figures
Figure
Number Title
Page
Number
13-18 ULPI Register Access (ULPI VIEWPORT)....................................................................... 13-23
13-19 Configure Flag Register (CONFIGFLAG)......................................................................... 13-24
13-20 Port Status and Control (PORTSC)..................................................................................... 13-25
13-21 OTG Status Control (OTGSC)............................................................................................ 13-30
13-22 USB Mode (USBMODE) ................................................................................................... 13-32
13-23 Endpoint Setup Status (ENDPTSETUPSTAT) ................................................................... 13-33
13-24 Endpoint Initialization (ENDPTPRIME)............................................................................ 13-34
13-25 Endpoint Flush (ENDPTFLUSH) ....................................................................................... 13-35
13-26 Endpoint Status (ENDPTSTATUS)..................................................................................... 13-35
13-27 Endpoint Complete (ENDPTCOMPLETE)........................................................................ 13-36
13-28 Endpoint Control 0 (ENDPTCTRL0) ................................................................................. 13-37
13-29 Endpoint Control 1 to 5 (ENDPTCTRLn).......................................................................... 13-38
13-30 Snoop 1 and Snoop 2 (SNOOPn)........................................................................................ 13-40
13-31 Age Count Threshold (AGE_CNT_THRESH)................................................................... 13-41
13-32 Priority Control (PRI_CTRL) ............................................................................................. 13-42
13-33 System Interface Control Register (SI_CTRL)................................................................... 13-42
13-34 USB General-Purpose Register (CONTROL).................................................................... 13-43
13-35 Periodic Schedule Organization.......................................................................................... 13-46
13-36 Frame List Link Pointer Format.......................................................................................... 13-47
13-37 Asynchronous Schedule Organization................................................................................ 13-48
13-38 Isochronous Transaction Descriptor (iTD) ......................................................................... 13-48
13-39 Split-Transaction Isochronous Transaction Descriptor (siTD) ........................................... 13-52
13-40 Queue Element Transfer Descriptor (qTD)......................................................................... 13-56
13-41 Queue Head Layout ............................................................................................................ 13-62
13-42 Frame Span Traversal Node Structure ................................................................................ 13-66
13-43 Derivation of Pointer into Frame List Array....................................................................... 13-72
13-44 General Format of Asynchronous Schedule List ................................................................ 13-73
13-45 Frame Boundary Relationship Between HS Bus and FS/LS Bus....................................... 13-73
13-46 Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries.............. 13-74
13-47 Example Periodic Schedule ................................................................................................ 13-76
13-48 Example Association of iTDs to Client Request Buffer..................................................... 13-79
13-49 Generic Queue Head Unlink Scenario................................................................................ 13-84
13-50 Asynchronous Schedule List with Annotation to Mark Head of List................................. 13-85
13-51 Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................... 13-87
13-52 Host Controller Asynchronous Schedule Split-Transaction State Machine ....................... 13-90
13-53 Split Transaction, Interrupt Scheduling Boundary Conditions........................................... 13-93
13-54 General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading .................... 13-94
13-55 Example Host Controller Traversal of Recovery Path via FSTNs...................................... 13-96
13-56 Split Transaction State Machine for Interrupt..................................................................... 13-99
13-57 Split Transaction, Isochronous Scheduling Boundary Conditions ................................... 13-106
13-58 siTD Scheduling Boundary Examples .............................................................................. 13-108