Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-41
Data cache queue sharing — The e300 has a new data cache queue sharing extension that
allows the two burst-write queues in the bus unit to be used
interchangeably for cache replacements and snoop pushes. Thus,
the data cache can support two outstanding cache replacements
or two outstanding snoop push operations on the bus at any given
time.
icbt instruction — The e300 supports a new instruction cache block touch instruction
that facilitates preloading the instruction cache before locking; the
G2_LE core requires speculatively fetching instructions before
locking the instruction cache.
1-½-level bus pipelining 1-level bus pipelining For the e300, a new transaction can complete an address tenure
when the previous transaction has been granted the data bus; for
the G2_LE, a new transaction must wait until the previous data
tenure has completed before completing its address tenure.
PowerPC little-endian not
supported
PowerPC little-endian
supported
PowerPC little-endian is not supported in the e300 core, although
true little-endian is fully supported.
Data retry mode removed Data retry mode available drtry
and drtrymode is no longer supported on the e300 and future
versions.
External control instructions
removed
External control instructions
available
The eciwx and ecowx instruction pair is not supported on the
e300 core. These are optional instructions in the PowerPC
architecture.
Reduced pin mode removed Reduced pin mode available Reduced pinout mode and the signal redpinmode is not supported
in the e300 core.
Table 7-9. Differences Between e300 and G2_LE Cores (continued)
e300 Core G2_LE Core Impact