Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-38 Freescale Semiconductor
address transfer, transfer attribute, address termination, data arbitration, data transfer, data termination, and
core state signals. Test and control signals provide diagnostics for selected internal circuits.
Figure 7-4. Core Interface
The core interface supports bus pipelining, allowing the address tenure of one transaction to overlap the
data tenure of another. The extent of the pipelining depends on external arbitration and control circuitry.
Similarly, the core supports split-bus transactions for systems with multiple potential bus masters; one
device can have mastership of the address bus while another has mastership of the data bus. Allowing
multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity
and, as a result, improves performance.
The core clocking structure allows the bus to operate at integer multiples of the core cycle time.
The following sections describe the core bus support for memory operations. Note that some signals
perform different functions depending on the addressing protocol used.
7.4.7.1 Memory Accesses
The e300 core CSB is a 64-bit data bus.
With a 64-bit CSB, memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus
clock cycle. Data transfers occur in either single-beat transactions or four-beat burst transactions.
Single-beat transactions are caused by noncached accesses that access memory directly (that is, reads and
writes when caching is disabled, caching-inhibited accesses, and stores in write-through mode). Four-beat
burst transactions, which always transfer an entire cache block (32 bytes), are initiated when a line is read
from or written to memory.
7.4.7.2 Signals
The e300 core signals are grouped as follows:
• Interrupts/Resets
e300 Core
1.5 V
Address Arbitration
Transfer Attribute
Address Transfer
Address Start
Clocks
Data Arbitration
Data Termination
Interrupt, Checkstops
Debug Control
JTAG/Debug Interface
Processor Status
Output Enable
Input Enable
Data Transfer
Address Termination
Test Interface
Reset
Debug Control