Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-37
an internal interrupt, the execution unit reports the interrupt to the completion/write-back pipeline
stage and discontinues instruction execution until the interrupt is handled. The interrupt is not
signaled until that instruction is the next to be completed. Execution of most floating-point
instructions is pipelined within the FPU, allowing up to three instructions to execute in the FPU
concurrently. The FPU pipeline stages are multiply, add, and round-convert. The LSU has two
pipeline stages: the first stage, for effective address calculation and MMU translation and the
second for accessing data in the cache.
• The complete/write-back pipeline stage maintains the correct architectural machine state and
transfers the contents of the rename registers to the GPRs and FPRs as instructions are retired. If
the completion logic detects an instruction causing an interrupt, all subsequent instructions are
canceled, their execution results in rename registers are discarded, and instructions are fetched
from the correct instruction stream.
A superscalar processor core issues multiple, independent instructions into multiple pipelines, allowing
instructions to execute in parallel. The e300c1 core has independent execution units for: integer
instructions, floating-point instructions, branch instructions, load/store instructions, and system register
instructions. The e300c3 provides two IUs, which improves the throughput of integer instructions. The
e300c3 provides two integer units for greater integer instruction throughput along with enhanced
multipliers in each IU that reduce the multiply instruction latency to a maximum of two cycles. The IU and
the FPU each have dedicated register files for maintaining operands (GPRs and FPRs, respectively),
allowing integer and floating-point calculations to occur simultaneously without interference.
The core provides support for single-cycle store, and it provides an adder/comparator in the system register
unit that allows the dispatch and execution of multiple integer add and compare instructions on each cycle.
Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction
timing among processor cores varies accordingly.
7.4.7 Core Interface
The core interface is specific for each processor core implementation.
The MPC8308 contains an internal coherent system bus (CSB) that interfaces the processor core to the
peripheral logic. In the case of the MPC8308, the CSB system logic decodes e300-initiated transactions
and directs all accesses to the appropriate interface.
The e300 core can operate at a variety of frequencies allowing the designer to trade off performance for
power consumption. The processor core is clocked from a separate PLL, which is referenced to the CSB
frequency. This allows the processor core and the peripheral logic to operate at different frequencies.
The e300 core provides a versatile core interface that allows for a wide range of implementations. The
interface includes a 32-bit address bus, a 64-bit data bus, and 56 control and information signals (see
Figure 7-4). The core interface allows for address-only transactions, as well as address and data
transactions. The core control and information signals include the address arbitration, address start,