Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-34 Freescale Semiconductor
External interrupt 00500 Caused when MSR[EE] = 1 and the int
signal is asserted.
Alignment 00600 Caused when the core cannot perform a memory access for any of the reasons described
below:
• The operand of a floating-point load or store instruction is not word-aligned.
• The operands of lmw, stmw, lwarx, and stwcx. instructions are not aligned.
• The instruction is lswi, lswx, stswi, stswx, and the core is in little-endian mode. Note
that PowerPC little-endian mode is not supported on the e300 core.
• The operand of dcbz is in memory that is write-through-required or caching-inhibited.
Program 00700 Caused by one of the following exception conditions, which correspond to bit settings in
SRR1 and arise during execution of an instruction.
Floating-point enabled exception—A floating-point enabled exception condition is
generated when the following condition is met:
(MSR[FE0] | MSR[FE1]) and FPSCR[FEX] is 1.
• FPSCR[FEX] is set by the execution of a floating-point instruction that causes an
enabled exception or by the execution of one of the Move to FPSCR instructions that
results in both an exception condition bit and its corresponding enable bit being set in
the FPSCR.
• Illegal instruction—An illegal instruction program interrupt is generated when execution
of an instruction is attempted with an illegal opcode or illegal combination of opcode and
extended opcode fields (including PowerPC instructions not implemented in the core),
or when execution of an optional instruction not provided in the core is attempted (these
do not include those optional instructions that are treated as no-ops).
• Privileged instruction—A privileged instruction program interrupt is generated when the
execution of a privileged instruction is attempted and the MSR register user privilege
bit, MSR[PR], is set. In the e300 core, this interrupt is generated for mtspr or mfspr with
an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all cores
that implement the PowerPC architecture.
• Trap—A trap type program interrupt is generated when any of the conditions specified
in a trap instruction are met.
Floating-point
unavailable
00800 Caused by an attempt to execute a floating-point instruction (including floating-point load,
store, and move instructions) when the floating-point available bit (MSR[FP]) is cleared.
Decrementer 00900 Occurs when DEC[0] changes from 0 to 1. This interrupt is enabled with MSR[EE].
Critical interrupt 00A00 Taken when cint
is asserted and MSR[CE] = 1.
Reserved 00B00–00BFF —
System call 00C00 Occurs when a System Call (sc) instruction is executed.
Trace 00D00 Taken when MSR[SE] =1 or when the currently completing instruction is a branch and
MSR[BE] =1.
Reserved 00E00 The e300 core does not generate an interrupt to this vector. Other devices may use this
vector for floating-point assist interrupts.
Performance
monitor
00F00 Caused when a configured PM counter using the pm_event_in to transition overflows.
Instruction
translation miss
01000 Caused when the effective address for an instruction fetch cannot be translated by the
ITLB.
Data load
translation miss
01100 Caused when the effective address for a data load operation cannot be translated by the
DTLB.
Table 7-8. Exceptions and Interrupts (continued)
Interrupt Type
Vector Offset
(hex)
Exception Conditions