Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-33
the e300 core, are caused by instructions. A system management interrupt is an implementation-specific
interrupt. The interrupt classes are shown in Table 7-7.
Although interrupts have other characteristics, such as whether they are maskable, the distinctions shown
in Table 7-7 define categories of interrupts that the core handles uniquely. Note that Table 7-7 includes no
synchronous, imprecise instructions. While the PowerPC architecture supports imprecise handling of
floating-point exceptions, the core implements floating-point exception modes as precise.
The e300 core interrupts and exception conditions that cause them are listed in Table 7-8.
Table 7-7. Interrupt Classifications
Synchronous/Asynchronous Precise/Imprecise Interrupt Type
Asynchronous, nonmaskable Imprecise Machine check
System reset
Asynchronous, maskable Precise External interrupt
Decrementer
System management interrupt
Critical interrupt
Synchronous Precise Instruction-caused interrupts
Table 7-8. Exceptions and Interrupts
Interrupt Type
Vector Offset
(hex)
Exception Conditions
Reserved 00000 —
System reset 00100 Caused by the assertion of either hreset
.
Machine check 00200 Caused by the assertion of the tea signal during a data bus transaction, assertion of mcp,
an address or data parity error, or an instruction or data cache parity error. Note that the
e300 has SRR1 register values that are different from the G2/G2_LE cores’ when a
machine check occurs.
DSI 00300 Determined by the bit settings in the DSISR, listed as follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of a DBAT register;
otherwise cleared
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared
6 Set for a store operation and cleared for a load operation
9 Set if a data address breakpoint interrupt occurs when the data [0–28] in the DABR or
DABR2 matches the next data access (load or store instruction) to complete in the
completion unit. The different breakpoints are enabled as follows:
• Write breakpoints enabled when DABR[30] is set
• Read breakpoints enabled when DABR[31] is set
ISI 00400 Caused when an instruction fetch cannot be performed for any of the following reasons:
• The effective (logical) address cannot be translated. That is, there is a page fault for this
portion of the translation, so an ISI interrupt must be taken to load the PTE (and possibly
the page) into memory.
• The fetch access violates memory protection (indicated by SRR1[4] set). If the key bits
(Ks and Kp) in the segment register and the PP bits in the PTE are set to prohibit read
access, instructions cannot be fetched from this location.