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e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-32 Freescale Semiconductor
To prevent the program state from being lost due to a system reset, a machine check interrupt or an
instruction-caused interrupt in the interrupt handler should save the information stored in SRR0 and SRR1
early and before enabling external interrupts.
The PowerPC architecture supports four types of interrupts:
• Synchronous, precise
These are caused by instructions. All instruction-caused interrupts are handled precisely; that is,
the machine state at the time the interrupt occurs is known and can be completely restored. This
means that (excluding the trap and system call interrupts) the address of the faulting instruction is
provided to the interrupt handler and neither the faulting instruction nor subsequent instructions in
the code stream completes execution before the interrupt is taken. Once the interrupt is processed,
execution resumes at the address of the faulting instruction (or at an alternate address provided by
the interrupt handler). When an interrupt is taken due to a trap or system call instruction, execution
resumes at an address provided by the handler.
• Synchronous, imprecise
The PowerPC architecture defines two imprecise floating-point exception modes: recoverable and
nonrecoverable. Even though the core provides a means to enable the imprecise modes, it
implements these modes identically to the precise mode (that is, all enabled floating-point
exceptions are always precise on the core).
• Asynchronous, maskable
The external system management interrupt (SMI) and decrementer interrupts are maskable,
asynchronous interrupts. When these interrupts occur, their handling is postponed until the next
instruction and any of its associated interrupts complete execution. If there are no instructions in
the execution units, the interrupt is taken immediately upon determination of the correct restart
address (for loading SRR0).
• Asynchronous, nonmaskable
The system reset and the machine check interrupt are nonmaskable, asynchronous interrupts. They
may not be recoverable, or they may provide a limited degree of recoverability. All interrupts report
recoverability through MSR[RI].
7.4.4.2 Implementation-Specific Interrupt Model
As specified by the PowerPC architecture, all interrupts can be described as either precise or imprecise and
either synchronous or asynchronous. Asynchronous interrupts (some of which are maskable) are caused
by events external to the processor’s execution; synchronous interrupts, which are all handled precisely by