Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xxvi Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
12-2 DMA Control Register (DMACR) ....................................................................................... 12-4
12-3 DMA Error Status Register (DMAES) ................................................................................. 12-7
12-4 DMA Enable Error Interrupt Register (DMAEEI) ............................................................... 12-8
12-5 DMA Set Enable Error Interrupt Register ............................................................................ 12-9
12-6 DMA Clear Enable Error Interrupt Register....................................................................... 12-10
12-7 DMA Clear Interrupt Request Register .............................................................................. 12-10
12-8 DMA Clear Error Register.................................................................................................. 12-11
12-9 DMA Set START Bit Register............................................................................................ 12-11
12-10 DMA Clear DONE Status Register..................................................................................... 12-12
12-11 DMA Interrupt Request Register Low (DMAINT) ............................................................ 12-13
12-12 DMA Error Register (DMAERR)....................................................................................... 12-14
12-13 DMA General Purpose Output Register (DMAGPOR)...................................................... 12-14
12-14 DMA Clear DONE Status Register..................................................................................... 12-16
12-15 TCD Word 0 (TCDn.saddr) Field ....................................................................................... 12-17
12-16 TCD Word 1 (TCDn.{soff, smod, ssize, dmod, dsize}) Fields........................................... 12-18
12-17 TCD Word 2 (TCD.{smloe, dmloe, nbytes}) Field ............................................................ 12-19
12-18 TCD Word 3 (TCDn.slast) Field......................................................................................... 12-19
12-19 TCD Word 4 (TCDn.daddr) Field....................................................................................... 12-20
12-20 TCD Word 5 (TCDn.{citer, doff}) Fields........................................................................... 12-20
12-21 TCD Word 6 (TCDn.dlast_sga) Field................................................................................. 12-21
12-22 TCD Word 7 (TCDn.{biter, control/status]) Fields ............................................................ 12-22
12-23 DMA Operation—Part 1..................................................................................................... 12-26
12-24 DMA Operation—Part 2..................................................................................................... 12-27
12-25 DMA Operation—Part 3..................................................................................................... 12-28
13-1 USB Interface Block Diagram .............................................................................................. 13-1
13-2 Capability Registers Length (CAPLENGTH)....................................................................... 13-6
13-3 Host Controller Interface Version (HCIVERSION) ............................................................. 13-7
13-4 Host Controller Structural Parameters (HCSPARAMS)....................................................... 13-7
13-5 Host Control Capability Parameters (HCCPARAMS) ......................................................... 13-8
13-6 Device Interface Version (DCIVERSION)........................................................................... 13-9
13-7 Device Control Capability Parameters (DCCPARAMS).................................................... 13-10
13-8 USB Command Register (USBCMD) ................................................................................ 13-10
13-9 USB Status Register (USBSTS).......................................................................................... 13-13
13-10 USB Interrupt Enable (USBINTR)..................................................................................... 13-15
13-11 USB Frame Index (FRINDEX)........................................................................................... 13-17
13-12 Periodic Frame List Base Address (PERIODICLISTBASE) ............................................. 13-18
13-13 Device Address (DEVICEADDR)...................................................................................... 13-19
13-14 Current Asynchronous List Address (ASYNCLISTADDR) .............................................. 13-19
13-15 Endpoint List Address (ENDPOINTLISTADDR).............................................................. 13-20
13-16 Master Interface Data Burst Size (BURSTSIZE) ............................................................... 13-21
13-17 Transmit FIFO Tuning Controls (TXFILLTUNING)......................................................... 13-22