Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-30 Freescale Semiconductor
The e300c3 data cache is configured as 128 sets of four blocks per set. The organization of the data cache
is shown in Figure 7-3.
Figure 7-3. e300c3 Data Cache Organization
Each cache block contains eight contiguous words from memory that are loaded from an 8-word boundary
(that is, bits A[27–31] of the effective addresses are zero); thus, a cache block never crosses a page
boundary. Misaligned accesses across a page boundary can incur a performance penalty.
The e300 core cache blocks are loaded in four beats of 64 bits each on the 64-bit data bus. The burst load
is performed as critical-double-word-first. The data cache is blocked to internal accesses until the load
completes; the instruction cache allows sequential fetching during a cache block load. In the core, the
critical-double-word is simultaneously written to the cache and forwarded to the requesting unit, thus
minimizing stalls due to load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the
core implements the MEI protocol during normal operation of the data cache. The new data cache MESI
extension supports the additional fourth cache coherency shared state for the data cache. To support this
feature, the shared signal, shd, has been added to the bus interface. Although the MESI protocol is
supported by the e300 core, it is not implemented on MPC8308. The following four states indicate the state
of the cache block:
• Modified—The cache block is modified with respect to system memory; that is, data for this
address is valid only in the cache and not in system memory.
• Exclusive—This cache block holds valid data that is identical to the data at this address in system
memory. No other cache has this data.
• Shared—Only available if HID2[MESISTATE] register bit is set. The address block is valid in the
cache and in at least one other cache. This block is always consistent with system memory. That is,
the shared state is shared-unmodified; there is no shared-modified state. Although the MESI
protocol is supported by the e300 core, it is not implemented on MPC8308.
• Invalid—This cache block does not hold valid data.
128 Sets
Block 1
Block 2
Block 3
Block 0
Address Tag 0
Address Tag 1
State
State
State
Words [0–7]
State
Words [0–7]
Words [0–7]
Words [0–7]
8 Words/Block
Address Tag 2
Address Tag 3