Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-25
Table 7-5 shows the bit definitions for HID1
Table 7-6 shows the bit definitions for HID2.
Table 7-5. HID1 Bit Descriptions
Bits Name Description
0 PC0 PLL configuration bit 0 (read-only)
1 PC1 PLL configuration bit 1 (read-only)
2 PC2 PLL configuration bit 2 (read-only)
3 PC3 PLL configuration bit 3 (read-only)
4 PC4 PLL configuration bit 4 (read-only)
5 PC5 PLL configuration bit 5 (read-only)
6 PC6 PLL configuration bit 6 (read-only)
7–31 — Reserved, should be cleared
Note: The clock configuration bits reflect the state of the pll_cfg[0:6] signals.
Table 7-6. e300HID2 Bit Descriptions
Bits Name Description
0–3 — Reserved, should be cleared.
4 LET True little-endian. This bit enables true little-endian mode operation for instruction and data accesses.
This bit is set to reflect the state of the tle signal at the negation of hreset
. This bit is used in
conjunction with MSR[LE] to determine the endian mode of operation.
0 No function
1 True little-endian mode, when MSR[LE] = 1
Changing the value of this bit during normal operation is not recommended
5 IFEB Instruction fetch burst extension. This bit enables the instruction fetch burst extension.
0 Instruction fetch burst extension disabled
1 Instruction fetch burst extension enabled
6 — Reserved, should be cleared.
7 MESISTATE MESI state enable. This bit enables the four-state MESI cache coherency protocol.
0 MESI disabled. The data cache uses a three-state MEI coherency protocol.
1 MESI enabled. The data cache uses a four-state MESI protocol.
8 IFEC Instruction fetch cancel extension. This bit enables the instruction fetch cancel extension.
0 Instruction fetch cancel extension disabled
1 Instruction fetch cancel extension enabled
9 EBQS Enable BIU queue sharing. This bit enables data cache queue sharing.
0 Data cache queue sharing disabled
1 Data cache queue sharing enabled
10 EBPX Enable BIU pipeline extension.This bit enables the bus interface unit pipeline extension.
0 BIU pipeline extension disabled; 1 level pipeline
1 BIU pipeline extension enabled; 1-1/2 level pipeline