Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-22 Freescale Semiconductor
Table 7-3 shows the bit definitions for HID0.
Table 7-3. e300 HID0 Bit Descriptions
Bits Name Function
0 EMCP Enable mcp
. The purpose of this bit is to mask out machine check interrupts caused by assertion of
mcp, similar to how MSR[EE] can mask external interrupts.
0 Masks mcp
. Asserting mcp does not generate a machine check interrupt or a checkstop.
1 Asserting mcp causes checkstop if MSR[ME] = 0 or a machine check interrupt if ME = 1
1 ECPE Enable cache parity errors.
0 Disables instruction and data cache parity error reporting
1 Allows a detected cache parity error to cause a machine check interrupt if MSR[ME] = 1 or a
checkstop if MSR[ME] = 0
2 EBA Enable ap_in[0:3] and ape
for address parity checking.
0 Disables address parity checking during a snoop operation
1 Allows an address parity error during snoop operations to cause a checkstop if MSR[ME] = 0 or a
machine check interrupt if MSR[ME] = 1
Note: Do not set this bit; the CSB does not have parity signals.
3 EBD Enable dpe
for data parity checking.
0 Disables data parity checking
1 Allows a data parity error during reads to cause a checkstop if MSR[ME] = 0 or a machine check
interrupt if MSR[ME] = 1
Note: Do not set this bit; the CSB does not have parity signals.
4 SBCLK clk_out output enable. Used in conjunction with HID0[ECLK] and hreset
to configure clk_out. See
Ta ble 7 -4 for settings.
5 — Reserved, should be cleared
6ECLKclk_out output enable. Used in conjunction with HID0[SBCLK] and the hreset signal to configure
clk_out. See Ta ble 7 -4 for settings.
7 PAR Disable precharge of artry_out
0 Precharge of artry_out enabled
1 Alters bus protocol slightly by preventing the processor from driving artry_out to high (negated) state.
If this is done, the integrated device must restore the signals to the high state.
8 DOZE Doze mode enable. Operates in conjunction with MSR[POW].
0 Doze mode disabled
1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is set. In doze mode,
the PLL, time base, and snooping remain active.
9 NAP Nap mode enable. Operates in conjunction with MSR[POW].
0 Nap mode disabled
1 Nap mode enabled. Nap mode is invoked by setting MSR[POW] while this bit is set. In nap mode, the
PLL and time base remain active.
10 SLEEP Sleep mode enable. Operates in conjunction with MSR[POW].
0 Sleep mode disabled
1 Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set. qreq
is
asserted to indicate that the processor is ready to enter sleep mode. If the system logic determines
that the processor may enter sleep mode, the quiesce acknowledge signal, qack
, is asserted back to
the processor. Once qack assertion is detected, the processor enters sleep mode after several
processor clocks. At this point, the system logic may turn off the PLL by first configuring pll_cfg[0:6]
to PLL bypass mode, then disabling sysclk.