Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xxv
Figures
Figure
Number Title
Page
Number
10-65 LCSn Signal Selection ........................................................................................................ 10-78
10-66 LBS Signal Selection .......................................................................................................... 10-79
10-67 UPM Read Access Data Sampling...................................................................................... 10-82
10-68 Effect of LUPWAIT Signal................................................................................................. 10-83
10-69 GPCM Address Timings..................................................................................................... 10-84
10-70 GPCM Data Timings........................................................................................................... 10-84
10-71 Interface to Different Port-Size Devices............................................................................. 10-85
10-72 Single-Beat Read Access to FPM DRAM .......................................................................... 10-91
10-73 Single-Beat Write Access to FPM DRAM ......................................................................... 10-93
10-74 Burst Read Access to FPM DRAM Using LOOP (Two Beats).......................................... 10-95
10-75 Refresh Cycle (CBR) to FPM DRAM ................................................................................ 10-97
10-76 Exception Cycle .................................................................................................................. 10-98
10-77 Interface to ZBT SRAM ................................................................................................... 10-100
11-1 System Connection of the eSDHC........................................................................................ 11-2
11-2 eSDHC Block Diagram......................................................................................................... 11-3
11-3 DMA System Address Register (DSADDR)........................................................................ 11-7
11-4 Block Attributes Register (BLKATTR) ................................................................................ 11-7
11-5 Command Argument Register (CMDARG) ......................................................................... 11-8
11-6 Transfer Type Register (XFERTYP)..................................................................................... 11-9
11-7 Command Response 0–3 Register (CMDRSPn) ................................................................ 11-12
11-8 Buffer Data Port Register (DATPORT) .............................................................................. 11-14
11-9 Present State Register (PRSSTAT)...................................................................................... 11-15
11-10 Protocol Control Register (PROCTL)................................................................................. 11-19
11-11 System Control Register (SYSCTL)................................................................................... 11-22
11-12 Interrupt Status Register (IRQSTAT).................................................................................. 11-25
11-13 Interrupt Status Enable Register (IRQSTATEN) ................................................................ 11-29
11-14 Interrupt Signal Enable Register (IRQSIGEN)................................................................... 11-31
11-15 Auto CMD12 Error Status Register (AUTOC12ERR)....................................................... 11-33
11-16 Host Capabilities Register (HOSTCAPBLT)...................................................................... 11-35
11-17 Watermark Level Register (WML)..................................................................................... 11-36
11-18 Force Event Register (FEVT) ............................................................................................. 11-37
11-19 Host Controller Version Register (HOSTVER) .................................................................. 11-38
11-20 eSDHC Buffer Scheme ....................................................................................................... 11-39
11-21 Example of Dividing a Large Data Transfer....................................................................... 11-41
11-22 DMA CSB Interface Block................................................................................................. 11-42
11-23 Command CRC Shift Register............................................................................................ 11-43
11-24 Two Stages of Clock Divider.............................................................................................. 11-44
11-25 a) Card Interrupt Scheme; b) Card Interrupt Detection and Handling Procedure .............. 11-46
11-26 Flow Diagram for Card Detection ...................................................................................... 11-48
11-27 Flow Chart for Reset of eSDHC and SD I/O Card ............................................................. 11-49
12-1 DMA Block Diagram............................................................................................................ 12-1