Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-18 Freescale Semiconductor
• XER register
The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field
specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store
String Word Indexed (stswx) instruction.
7.4.1.2 VEA Registers
The VEA introduces the time base facility (TB) for reading. The TB is a 64-bit register pair whose contents
are incremented once every four core input clock cycles. The TB consists of two 32-bit registers—time
base upper (TBU) and time base lower (TBL). Note that the time base registers are read-only in user state.
7.4.1.3 OEA Registers
OEA registers are supervisor-level registers that include the following.
7.4.1.3.1 Machine State Register (MSR)
The MSR is a supervisor-level register that defines the state of the core. The contents of this register are
saved when an interrupt is taken, and restored when the interrupt handling completes. A critical interrupt
interrupt is taken in the e300 core when the cint signal is asserted and MSR[CE] is set. The e300 core
implements the MSR as a 32-bit register.
Table 7-2 shows the bit definitions for MSR.
Table 7-2. MSR Bit Descriptions
Bits Name Description
0
1
— Reserved. Full function.
1–4
1
— Reserved. Partial function.
5–9
1
— Reserved. Full function.
10–12
1
— Reserved. Partial function.
13 POW Power management enable (implementation-specific)
0 Disables programmable power modes (normal operation mode)
1 Enables programmable power modes (nap, doze, or sleep mode).
This bit controls the programmable power modes only; it has no effect on dynamic power management (DPM).
MSR[POW] may be altered with an mtmsr instruction only. Also, when altering the POW bit, software may alter
only this bit in the MSR and no others. The mtmsr instruction must be followed by a context-synchronizing
instruction.
14 TGPR Temporary GPR remapping (implementation-specific)
0 Normal operation
1 TGPR mode. GPR0–GPR3 are remapped to TGPR0–TGPR3 for use by TLB miss routines.
The contents of GPR0–GPR3 remain unchanged while MSR[TGPR] = 1. Attempts to use GPR4–GPR31 with
MSR[TGPR] = 1 yield undefined results. Temporarily replaces TGPR0–TGPR3 with GPR0–GPR3 for use by
TLB miss routines. The TGPR bit is set when either an instruction TLB miss, data read miss, or data write miss
interrupt is taken. The TGPR bit is cleared by an rfi instruction.
15 ILE Interrupt little-endian mode. When an interrupt occurs, this bit is copied into MSR[LE] to select the endian
mode for the context established by the interrupt.