Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-13
— The performance monitor counter registers (PMC0–PMC3) are 32-bit counters used to count
software-selectable events. Each counter counts up to 128 events. UPMC0–UPMC3 provide
user-level read access to these registers. They are identified in Table 7-2.
— The performance monitor global control register (PMGC0) controls the counting of
performance monitor events. It takes priority over all other performance monitor control
registers. UPMGC0 provides user-level read access to PMGC0.
— The performance monitor local control registers (PMLCa0–PMLCa3) control each individual
performance monitor counter. Each counter has a corresponding PMLCa register.
UPMLCa0–UPMLCa3 provide user-level read access to PMLCa0–PMLCa3).
• The performance monitor interrupt is assigned to interrupt vector 0x0F00.
Software communication with the performance monitor is achieved through PMRs rather than SPRs. The
PMRs are used for enabling conditions that can trigger the performance monitor interrupt.
7.2 e300 Processor and System Version Numbers
Table 7-1 lists the revision codes in the processor version register (PVR) and the system version register
(SVR) to the revision level marked on the device. These registers can be accessed as SPRs through the
e300 core (see Figure 7-2).
7.3 PowerPC Architecture Implementation
The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can
be measured in terms of which of the following levels of the architecture is implemented:
• User instruction set architecture (UISA)
Defines the base user-level instruction set, user-level registers, data types, floating-point interrupt
model, memory models for a uniprocessor environment, and programming model for a
uniprocessor environment.
• Virtual environment architecture (VEA)
Describes the memory model for a multiprocessor environment, defines cache control instructions,
and describes other aspects of virtual environments. Implementations that conform to the VEA also
adhere to the UISA but may not necessarily adhere to the OEA.
• Operating environment architecture (OEA)
Defines the memory management model, supervisor-level registers, synchronization requirements,
and interrupt model. Implementations that conform to the OEA also adhere to the UISA and VEA.
The PowerPC architecture allows a wide range of designs for such features as cache and core interface
implementations.
Table 7-1. Device Revision Level Cross-Reference
MPC8308 Revision Processor Version Register (PVR) System Version Register (SVR)
1.1 8085_0020 8101_0111
1.0 8085_0020 8101_0110