Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xxiv Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
10-36 GPCM Basic Write Timing
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = 2, 4, 8).............. 10-47
10-37 GPCM Relaxed Timing Back-to-Back Reads
(XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8)10-49
10-38 GPCM Relaxed Timing Back-to-Back Writes
(XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8).................. 10-49
10-39 GPCM Relaxed Timing Write
(XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1, CLKDIV = 4, 8).................. 10-50
10-40 GPCM Relaxed Timing Write
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1, CLKDIV = 4, 8).................. 10-50
10-41 GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)......................... 10-51
10-42 GPCM Read Followed by Write
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads) ............................ 10-51
10-43 External Termination of GPCM Access.............................................................................. 10-52
10-44 Local Bus to 8-Bit FCM Device Interface.......................................................................... 10-54
10-45 FCM Basic Page Read Timing
(PGS = 1, CSCT = 0, CST = 0, CHT = 1, RST = 1, SCY = 0, TRLX = 0, EHTR = 1) 10-54
10-46 FCM Buffer RAM Memory Map for Small-Page (512-byte page) NAND Flash Devices 10-56
10-47 FCM Buffer RAM Memory Map for Large-Page (2-Kbyte page) NAND Flash Devices . 10-57
10-48 FCM ECC Calculation........................................................................................................ 10-57
10-49 ECC Placement in NAND Flash Spare Regions in Relation to FMR[ECCM] .................. 10-58
10-50 FCM Instruction Sequencer Mechanism............................................................................. 10-59
10-51 Timing of FCM Command/Address and Write Data Cycles
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)................................... 10-62
10-52 Example of FCM Command and Address Timing with Minimum Delay Parameters
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0, CLKDIV = 4*N)................................... 10-63
10-53 Example of FCM Command and Address Timing with Relaxed Parameters
(for TRLX = 1, CHT = 0, CST = 1, SCY = 2, CLKDIV = 4*N)................................... 10-63
10-54 FCM Delay Prior to Sampling LFRB
State ........................................................................ 10-64
10-55 FCM Read Data Timing
(for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N)................................................... 10-64
10-56 FCM Read Data Timing with Extended Hold Time
(for TRLX = 0, EHTR = 1, RST = 1, SCY = 1, CLKDIV = 4*N) ................................ 10-65
10-57 FCM Buffer RAM Memory Map During Boot Loading .................................................... 10-67
10-58 User-Programmable Machine Functional Block Diagram.................................................. 10-68
10-59 RAM Array Indexing.......................................................................................................... 10-69
10-60 Memory Refresh Timer Request Block Diagram ............................................................... 10-70
10-61 UPM Clock Scheme for LCRR[CLKDIV] = 2................................................................... 10-73
10-62 UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8 ........................................................... 10-74
10-63 RAM Array and Signal Generation .................................................................................... 10-74
10-64 RAM Word Fields............................................................................................................... 10-75