Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-11
noncacheable access is performed), and provides support for a write operation to proceed a previously
queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data
tenures of a read operation). Because the processor can dynamically optimize run-time ordering of
load/store traffic, overall performance is improved.
7.1.7 System Support Functions
The e300 core implements several support functions that include power management, time
base/decrementer registers for system timing tasks, a JTAG (based on IEEE Std 1149.1™) interface,
hardware debug, and a phase-locked loop (PLL) clock multiplier. These system support functions are
described in the following sections.
7.1.7.1 Power Management
The e300 core provides four power modes, selectable by setting the appropriate control bits in the machine
state register (MSR) and the hardware implementation register 0 (HID0). When entering into a power
mode other than full-power, the core requests entry via a qreq signal and enters another power mode after
an acknowledge (qack) is received. The four power modes are as follows:
• Full-power
This is the default power state of the e300 core. The e300 core is fully powered and the internal
functional units are operating at the full processor clock speed. If the dynamic power management
mode is enabled, functional units that are idle automatically enters a low-power state without
affecting performance, software execution, or external hardware.
• Doze
All the functional units of the e300 core are disabled except for the time base/decrementer registers
and the bus snooping logic. When the processor is in doze mode, an external asynchronous
interrupt, system management interrupt, decrementer interrupt, hard or soft reset, or machine check
brings the e300 core into the full-power state. The core in doze mode maintains the PLL in a
fully-powered state and locked to the system external clock input (sysclk), so a transition to the
full-power state takes only a few processor clock cycles.
•Nap
The nap mode further reduces power consumption by disabling bus snooping, leaving only the time
base register and the PLL in a powered state. The core returns to the full-power state on receipt of
an external asynchronous interrupt, system management interrupt, decrementer interrupt, hard or
soft reset, or machine check input (mcp
) signal. A return to full-power state from a nap state takes
only a few processor clock cycles.
•Sleep
Sleep mode reduces power consumption to a minimum by disabling all internal functional units;
then external system logic may disable the PLL and sysclk. Returning the core to the full-power
state requires the enabling of the PLL and sysclk, followed by the assertion of an external
asynchronous interrupt, system management interrupt, hard or soft reset, or mcp signal after the
time required to relock the PLL.