Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-5
• Integrated power management
— Internal processor/bus clock multiplier ratios
— Three power-saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• In-system testability and debugging features through JTAG boundary-scan capability
Features specific to the e300 core not present on the G2 processors follow:
• Enhancements to the register set
— The e300 core has one more HID0 bit than the G2:
– The enable cache parity checking (ECPE) bit, HID0[1], gives the e300 core the ability to
enable the taking of a machine check interrupt based on the detection of a cache parity error
• Enhancements to cache implementation
— 16-Kbyte, four-way set-associative instruction and data caches on the e300c3.
— Full parity checking is performed on both instruction and data cache memory arrays
— Lockable L1 instruction and data caches—entire cache or on a per-way basis up to 3 of 4 ways
on the e300c3
—New icbt instruction supports initialization of instruction cache
— Data cache supports four-state MESI coherency protocol (not implemented on MPC8308)
— The instruction cache is blocked only until the critical load completes (hit under reloads
allowed)
— Instruction cancel mechanism improves utilization of instruction cache by supporting
hits-under-cancels and misses-under-cancels.
— The critical double word is simultaneously written to the cache and forwarded to the requesting
unit, thus minimizing stalls due to load delays.
— Data cache queue sharing makes cast-outs and snoop pushes more efficient
— Provides for an optional data cache operation broadcast feature (enabled by HID0[ABE]) that
allows for coherent system management. All of the data cache control instructions, except dcbz
(dcbi, dcbf, and dcbst) require that HID0[ABE] be enabled to broadcast.
— Instruction fetch burst feature allows all instruction fetches from caching-inhibited space to be
performed on the bus as burst transactions
• Interrupts
— The e300 core offers hardware support for misaligned little-endian accesses. Little-endian
load/store accesses that are not on a word boundary, except for strings and multiples, generate
interrupts under the same circumstances as big-endian accesses.
— The e300 core supports true little-endian mode to minimize the impact on software porting
from true little-endian systems.
— An input interrupt signal, cint, is provided to trigger the critical interrupt exception on the e300
core. The pm_event_in input signal can be used by the performance monitor counters to trigger
an interrupt upon overflow on the e300c3 .
• Bus clock—PLL configuration signals include seven signals for settings and control: pll_cfg[0:6].