Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-3
The e300c3 includes 16-Kbyte, four way set-associative instruction and data caches. The MMUs contain
64-entry, two-way, set-associative, data and instruction translation lookaside buffers (DTLB and ITLB)
that provide support for demand-paged, virtual-memory, address translation, and variable-sized block
translation. The TLBs use a least recently used (LRU) replacement algorithm and the caches use a pseudo
least recently used algorithm (PLRU).
The core also supports block address translation through the use of two independent instruction and data
block address translation (IBAT and DBAT) arrays, each containing eight pairs of BATs, an increase from
four pairs of each type of BATs in the G2 core. This increase provides more flexibility in protecting
accesses and providing translation on a segment, block, or page basis for memory accesses and I/O
accesses. Effective addresses are compared simultaneously with all eight entries in the BAT array during
block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB
and BAT array, the BAT translation takes priority.
As part of the coherent system bus (CSB), the e300 core has a 64-bit data bus and a 32-bit address bus.
During normal operation, the e300 core provides a three-state (modified, exclusive, and invalid) coherency
protocol which is a compatible subset of a four-state (modified/exclusive/shared/invalid) MESI protocol.
However, the e300 data cache contains a programmable MESI extension that supports the shared cache
coherency state (similar to other PowerPC processors). Both protocols operate coherently in systems that
contain four-state caches. Although MESI is supported by the e300 core, it is not implemented on the
MPC8308. The core also supports single-beat and burst data transfers for memory accesses and supports
memory-mapped I/O operations.
The true little-endian mode is another enhanced capability of the e300 core. Unlike the PowerPC
little-endian mode (which manipulates only the address bits), no longer supported on the e300, the true
little-endian mode actually operates on true little-endian instructions and data from memory.
The critical interrupt is an additional interrupt in the e300 core and has higher priority order than the
system management interrupt. Also, debug features are improved in the e300. Additional SPRG interrupt
handling registers are provided for enhancing flexibility for the operating system.
The e300c3 include a performance monitor facility that provides the ability to monitor and count
predefined events such as core clocks, misses in the instruction cache, data cache, types of instructions
dispatched, mispredicted branches, and other occurrences. The count of such events (which may be an
approximation) can be used to trigger the performance monitor interrupt. Section 7.1.7.5, “Core
Performance Monitor,” describes the operation of the performance monitor diagnostic tool.
7.1.1 Features
This section describes the major features of the e300 core:
• High-performance, superscalar microprocessor core
— As many as three instructions issued and retired per clock (two instructions plus one branch
instruction)
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined floating-point unit (FPU) for all single- and double-precision operations