Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-2 Freescale Semiconductor
Figure 7-1 shows a block diagram of the e300c3 core. Note that the e300c3 supports floating-point
operations and includes two integer units.
Figure 7-1. e300c3 Core Block Diagram
64-Bit
64-Bit (Two Instructions)
32-Bit
Branch
Processing
Unit
64-Bit Data Bus
32-Bit Address Bus
Instruction Unit
Integer
Unit1
16-Kbyte
D Cache
Tags
Sequential
Fetcher
CTR
CR
LR
System
Register
Unit
+
*
/
Core Interface
D MMU
SRs
DTLB
DBAT
Array
Touch Load Buffer
Copy-Back Buffer
64-Bit
Dispatch Unit
64-Bit (Two Instructions)
Power
Dissipation
Control
Completion
Unit
Time Base
Counter/
Decrementer
PLL & Clock
Multiplier
Debug/COP
JTAG Interface
XER
I MMU
SRs
ITLB
IBAT
Array
16-Kbyte
I Cache
Tag s
64-Bit
32-Bit
GPR File
Load/Store
Unit
+
64-Bit
GP Rename
Registers
Instruction
Queue
+
Completes up to
two instructions
per clock
Integer
Unit2
+
*
/
XER
64-Bit
FPR File
FP Rename
Registers
Floating-
Point Unit
+
*
/
FPSCR
Performance Monitor