Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xxiii
Figures
Figure
Number Title
Page
Number
9-39 Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-52
9-40 Write Timing Adjustments Example for Write Latency = 1................................................. 9-53
9-41 DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 9-54
9-42 DDR SDRAM Power-Down Mode ...................................................................................... 9-55
9-43 DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-56
9-44 DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-56
10-1 Enhanced Local Bus Controller Block Diagram................................................................... 10-1
10-2 Base Registers (BRn)............................................................................................................ 10-9
10-3 Option Registers (ORn) in GPCM Mode............................................................................ 10-12
10-4 Option Registers (ORn) in FCM Mode............................................................................... 10-14
10-5 Option Registers (ORn) in UPM Mode .............................................................................. 10-17
10-6 UPM Memory Address Register (MAR)............................................................................ 10-18
10-7 UPM Mode Registers (MxMR)........................................................................................... 10-19
10-8 Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 10-21
10-9 UPM Data Register in UPM Mode (MDR) ........................................................................ 10-22
10-10 FCM Data Register in FCM Mode (MDR)......................................................................... 10-22
10-11 Special Operation Initiation Register (LSOR).................................................................... 10-23
10-12 UPM Refresh Timer (LURT) .............................................................................................. 10-23
10-13 Transfer Error Status Register (LTESR) ............................................................................. 10-24
10-14 Transfer Error Check Disable Register (LTEDR)............................................................... 10-26
10-15 Transfer Error Interrupt Enable Register (LTEIR).............................................................. 10-27
10-16 Transfer Error Attributes Register (LTEATR) .................................................................... 10-28
10-17 Transfer Error Address Register (LTEAR) ......................................................................... 10-29
10-18 Transfer Error ECC Register (LTECCR) ............................................................................ 10-29
10-19 Local Bus Configuration Register....................................................................................... 10-30
10-20 Clock Ratio Register (LCRR)............................................................................................. 10-31
10-21 Flash Mode Register ........................................................................................................... 10-32
10-22 Flash Instruction Register ................................................................................................... 10-34
10-23 Flash Command Register.................................................................................................... 10-35
10-24 Flash Block Address Register............................................................................................. 10-36
10-25 Flash Page Address Register, Small Page Device (ORx[PGS] = 0)................................... 10-36
10-26 Flash Page Address Register, Large Page Device (ORx[PGS] = 1)................................... 10-36
10-27 Flash Byte Count Register .................................................................................................. 10-38
10-28 Flash ECC Blockn Register (FECC0–FECC3)................................................................... 10-38
10-29 Basic Operation of Memory Controllers in the eLBC ........................................................ 10-40
10-30 Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0)........ 10-41
10-31 Basic eLBC Bus Cycle with TA, and LCSn ....................................................................... 10-41
10-32 Enhanced Local Bus to GPCM Device Interface................................................................ 10-42
10-33 GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8).............. 10-43
10-34 GPCM General Read Timing Parameters........................................................................... 10-43
10-35 GPCM General Write Timing Parameters .......................................................................... 10-45