Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 6-17
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.5 Reserved Transaction Type
Table 6-12 shows transaction types defined as reserved.
For the transaction with a reserved transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[RES].
3. Issues reset request, MCP or regular interrupt according to AERR[RES] and AIDR[RES], if
enabled by AMR[RES].
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.6 Illegal (eciwx/ecowx) Transaction Type
Table 6-13 shows transaction types defined as illegal.
For the transaction with an illegal (eciwx, ecowx) transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK
.
2. Starts data tenure and ends data tenure by asserting TEA.
3. Reports on the event in AER[ECW].
4. Issues reset request, MCP or regular interrupt according to AERR[ECW] and AIDR[ECW], if
enabled by AMR[ECW].
5. Updates transaction attributes and address of AEATR and AEADR for the first error event.
For more information, see the following sections:
• Section 6.2.4, “Arbiter Event Register (AER)”
• Section 6.2.5, “Arbiter Interrupt Definition Register (AIDR)”
• Section 6.2.6, “Arbiter Mask Register (AMR)”
• Section 6.2.7, “Arbiter Event Attributes Register (AEATR)”
Table 6-12. Reserved Transaction Type Encoding
ttype[0:4] Bus Commands
00101 Reserved
1xx01 Reserved for customer
10110 Reserved
00011 Reserved
00111 Reserved
01111 Reserved
1xx11 Reserved for customer
Table 6-13. Illegal Transaction Type Encoding
ttype[0:4] Bus command
10100 External control word write (ecowx)
11100 External control word read (eciwx)