Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
6-16 Freescale Semiconductor
6.3.2.2 Data Time Out
Data time out occurs, if the data tenure was not ended before the specified time-out period (programmed
by ATR[DTO]). In this case, the arbiter performs as follows:
1. Ends the data tenure by asserting transfer error.
2. Reports on this event in AER[DTO].
3. Issues reset request, MCP or regular interrupt according to AERR[DTO] and AIDR[DTO], if
enabled by AMR[DTO].
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.3 Transfer Error
The arbiter tracks the transfer error asserted by one of the slaves. In this case, the arbiter performs as
follows:
1. Reports on the event to AER[ETEA].
2. Issues reset request, MCP or regular interrupt according to AERR[ETEA] and AIDR[ETEA] if
enabled by AMR[ETEA].
3. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.4 Address Only Transaction Type
Table 6-11 shows transaction types that are defined as address only:
The arbiter allows address-only (AO) transactions on the bus, and the G2 core has ability to issue
address-only (AO) transactions (see HID0 [ABE] in the G2 PowerPC Core Reference Manual, Rev 1). As
there is no advantage in using AO transaction in this system, the bus monitor allows the detection of AO
transactions and treats them as an error.
For the transaction with an address-only transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[AO].
3. Issues reset request, MCP or regular interrupt according to AERR[AO] and AIDR[AO] if enabled
by AMR[AO].
Table 6-11. Address Only Transaction Type Encoding
ttype[0:4] Bus Commands
00000 Clean block
00100 Flush block
01000 Sync
01100 Kill block
10000 eieio
11000 TLB Invalidate
00001 lwarx reservation set
01001 tlbsync
01101 icbi