Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 6-15
completion of snoop copyback, the arbiter grants the bus back to the master that had its transaction
ARTRYed.
6.3.1.4 Address Bus Parking
The arbiter supports address bus parking. This feature implies that when no master is requesting the bus
(all bus requests are negated), the arbiter can choose to park the address bus (or assert the address bus
grant) to a master. The parked master can skip the bus request and assume the bus mastership directly. This
reduces the access latency for parked master.
See Section 6.2.1, “Arbiter Configuration Register (ACR),” for more details about ACR[APARK] and
ACR[PARKM].
6.3.1.5 Data Bus Arbitration
For every committed address tenure a data tenure is required to complete the transaction.
In the device system, the arbiter controls the issuing of data bus grants to a master and a slave, which are
involved in a data tenure of a previously performed address tenure.
6.3.2 Bus Error Detection
The arbiter is responsible for tracking the following cases on the bus:
• Address time out
• Data time out
• Transfer error
• Address only transaction type
• Reserved transaction type
• Illegal (eciwx/ecowx) transaction type
6.3.2.1 Address Time Out
Address time out occurs, if the address tenure was not ended before the specified time-out period
(programmed by ATR[ATO]). In this case, the arbiter performs as follows:
1. Ends the address tenure.
2. Starts data tenure and ends it by asserting transfer error.
3. Reports on the event to AER[ATO].
4. Issues reset request, MCP or regular interrupt according to AERR[ATO] and AIDR[ATO], if
enabled by AMR[ATO].
5. Updates transaction attributes and address of AEATR and AEADR for the first error event.