Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
6-14 Freescale Semiconductor
Figure 6-11. An Example of Priority-Based Arbitration Algorithm
NOTE
See each bus master’s chapter and Section 5.2.2.4, “System Priority and
Configuration Register (SPCR),” for more details about priority
programming.
6.3.1.2 Address Bus Arbitration with REPEAT
When a master owns the address bus and wants to perform another transaction, it can assert bus request
along with REPEAT
to make a repeat request to the arbiter. Consequently, the arbiter asserts bus grant to
the same master if the current address tenure is not being ARTRY
ed. This happens regardless of the priority
level of bus request from other masters. In another word, “repeat request” overrides the priority scheme.
Even though repeat request can improve the page hit ratio and the overall memory bandwidth efficiency,
it can increase the worst-case latency of individual master. Therefore, the arbiter has programmable
counter to limit the maximum number of consecutive transactions that are performed by masters.
Whenever the counter expires, the arbiter ignores the REPEAT signal and falls back to the regular
arbitration scheme.
6.3.1.3 Address Bus Arbitration after ARTRY
The ARTRY protocol is used primarily by the CPU to interrupt a transaction that hits to a modified line in
its D-cache, so that it can maintain data coherency by performing the snoop copyback. When the CPU
asserts ARTRY, the bus is immediately granted to the CPU to perform snoop copyback. After the
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