Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 6-13
A master has to acquire address bus ownership before it starts any transaction. The master asserts its own
bus request signal along with the arbitration attribute signals REPEAT and PRIORITY[0:1]. The arbiter
later asserts the corresponding address bus grant signal to the requesting master depending on the system
states and arbitration scheme. See Section 6.3.1.1, “Address Bus Arbitration with PRIORITY[0:1],” for
details on arbitration scheme. When address bus grant is received the master can start the address tenure.
6.3.1.1 Address Bus Arbitration with PRIORITY[0:1]
Whenever a master asserts its bus request to acquire address bus ownership, it can drive its
PRIORITY[0:1] signals to indicate request priority. The master would be served sooner because of its
higher priority level. The arbiter takes this extra information into consideration in order to yield better
service for a higher priority request than a lower priority request. Therefore, the arbiter operates according
to the following priority-based arbitration scheme:
1. For every priority level a fair arbitration scheme is used (a simple round-robin scheme)
2. For every priority level other than 0, one place is reserved as a place-holder for lower level
arbitration rings.
3. Each master can change its priority level at any time.
Figure 6-11 shows an example of priority-based arbitration algorithm with four priority levels. In this
example, if all masters request the bus continuously, the following order of bus grants occurs with the
specific bandwidth:
• M6 gets ½ of the bus bandwidth
• M4 and M5 each gets 1/6 of the bus bandwidth
• M0 and M3 each gets 1/18 of the bus bandwidth
• M1 and M2 each gets 1/36 of the bus bandwidth