Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
6-12 Freescale Semiconductor
6.3 Functional Description
The following sections describe arbitration policy and bus error detection.
6.3.1 Arbitration Policy
The arbitration process involves the masters and the arbiter. Masters arbitrate on the privilege to own an
address tenure. For data tenures, the arbiter uses the same order of transactions as address tenures.
Figure 6-10 shows the interface signals between the arbiter and masters that are involved in address bus
arbitration.
Figure 6-10. Address Bus Arbitration
28 ECW External control word transfer type. Transaction with external control word transfer type interrupt
definition.
0 Transaction with external control word transfer type causes interrupt.
1 Transaction with external control word transfer type causes reset request.
29 AO Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes interrupt.
1 Transaction with address only transfer type causes reset request.
30 DTO Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes interrupt.
1 Data tenure time out causes reset request.
31 ATO Address time out. Address tenure time out interrupt definition.
0 Address tenure time out causes interrupt.
1 Address tenure time out causes reset request.
Table 6-10. AERR Field Descriptions
Bits Name Description
BR
Arbiter
Master 2
REPEAT
PRIORITY[0:1]
BG
BR
REPEAT
PRIORITY[0:1]
BG
Master N
BR
REPEAT
PRIORITY[0:1]
BG
Master 1
•
•
•