Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 6-11
failure had caused a deadlock situation. For more information, see Section 6.4.2, “Error Handling
Sequence.”
Figure 6-8 shows the fields of AEADR.
Table 6-9 describes AEADR fields.
6.2.9 Arbiter Event Response Register (AERR)
The arbiter event response register (AERR) determines whether different error conditions cause interrupt
or reset request. Setting a bit defines the corresponding error condition to cause reset request; clearing a
bit defines the corresponding error condition to cause interrupt. Figure 6-9 shows the fields of AERR.
Table 6-10 describes AERR field.
Offset 0x1C Access: Read only
0 31
R
ADDR
W
Reset All zeros
Figure 6-8. Arbiter Event Address Register (AEADR)
Table 6-9. AEADR Field Descriptions
Bits Name Description
0–31 ADDR Address of the event reported in AEATR register. See Section 6.2.7, “Arbiter Event Attributes Register
(AEATR),” for more information.
Offset 0x20 Access: User read/write
0 25 26 27 28 29 30 31
R
— ETEA RES ECW AO DTO ATO
W
Reset All zeros
Figure 6-9. Arbiter Event Response Register (AERR)
Table 6-10. AERR Field Descriptions
Bits Name Description
0–25 — Write reserved, read = 0
26 ETEA Transfer error. Detection of transfer error by one of the slaves event response.
0 Detection of transfer error by one of the slaves causes interrupt.
1 Detection of transfer error by one of the slaves causes reset request.
27 RES Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes interrupt.
1 Transaction with reserved transfer type causes reset request.