Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xxii Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
8-31 Message Shared Interrupt Mask Register (MSIMR) ............................................................ 8-41
8-32 Message Shared Interrupt Status Register (MSISR)............................................................. 8-42
8-33 Message Shared Interrupt Index Register (MSIIR) .............................................................. 8-43
9-1 DDR Memory Controller Simplified Block Diagram............................................................. 9-2
9-2 Chip Select Bounds Registers (CSn_BNDS)........................................................................ 9-11
9-3 Chip Select Configuration Register (CSn_CONFIG)........................................................... 9-12
9-4 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................................ 9-13
9-5 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................................ 9-14
9-6 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................................ 9-16
9-7 DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 9-18
9-8 DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG).............................. 9-19
9-9 DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 9-22
9-10 DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 9-23
9-11 DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)...................... 9-24
9-12 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................................ 9-25
9-13 DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 9-27
9-14 DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 9-28
9-15 DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)....... 9-28
9-16 DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-29
9-17 DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-29
9-18 DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-30
9-19 Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI)......... 9-30
9-20 Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)......... 9-31
9-21 Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)............................ 9-31
9-22 Memory Data Path Read Capture High Register (CAPTURE_DATA_HI).......................... 9-32
9-23 Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO) ......................... 9-32
9-24 Memory Data Path Read Capture ECC Register (CAPTURE_ECC)................................... 9-33
9-25 Memory Error Detect Register (ERR_DETECT)................................................................. 9-33
9-26 Memory Error Disable Register (ERR_DISABLE).............................................................. 9-34
9-27 Memory Error Interrupt Enable Register (ERR_INT_EN)................................................... 9-35
9-28 Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)........................... 9-36
9-29 Memory Error Address Capture Register (CAPTURE_ADDRESS) ................................... 9-37
9-30 Single-Bit ECC Memory Error Management Register (ERR_SBE) .................................... 9-37
9-31 Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-39
9-32 Typical DDR SDRAM Interface Signals .............................................................................. 9-39
9-33 Example 64-Mbyte DDR SDRAM Configuration With ECC.............................................. 9-41
9-34 DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-49
9-35 DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 9-49
9-36 DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 9-50
9-37 DDR SDRAM Clock Distribution Example for 8 DDR SDRAMs.................................... 9-50
9-38 DDR SDRAM Mode-Set Command Timing........................................................................ 9-51