Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
6-8 Freescale Semiconductor
6.2.6 Arbiter Mask Register (AMR)
The arbiter mask register (AMR) is used to mask interrupts or reset requests. Setting a mask bit enables
the corresponding interrupt or reset request; clearing a bit masks it. Regular interrupts, MCP interrupts,
and reset requests can be masked by AMR register. Figure 6-6 shows the fields of AMR.
Table 6-7 describes AMR fields.
28 ECW External control word transfer type. Transaction with external control word transfer type interrupt definition.
0 Transaction with external control word transfer type causes regular interrupt.
1 Transaction with external control word transfer type causes MCP interrupt.
29 AO Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes regular interrupt.
1 Transaction with address only transfer type causes MCP interrupt.
30 DTO Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes regular interrupt.
1 Data tenure time out causes MCP interrupt.
31 ATO Address time out. Address tenure time out interrupt definition.
0 Address tenure time out causes regular interrupt.
1 Address tenure time out causes MCP interrupt.
Offset 0x14 Access: User read/write
0 25 26 27 28 29 30 31
R
— ETEA RES ECW AO DTO ATO
W
Reset All zeros
Figure 6-6. Arbiter Mask Register (AMR)
Table 6-7. AMR Field Descriptions
Bits Name Description
0–25 — Write reserved, read = 0
26 ETEA Transfer error. Detection of transfer error by one of the slaves interrupt mask bit.
0 Detection of transfer error by one of the slaves interrupt disabled.
1 Detection of transfer error by one of the slaves interrupt enabled.
27 RES Reserved transfer type.Transaction with reserved transfer type interrupt mask bit.
0 Transaction with reserved transfer type interrupt disabled.
1 Transaction with reserved transfer type interrupt enabled.
28 ECW External control word transfer type.Transaction with external control word transfer type interrupt mask bit.
0 Transaction with external control word transfer type interrupt disabled.
1 Transaction with external control word transfer type interrupt enabled.
29 AO Address only transfer type. Transaction with address only transfer type interrupt mask bit.
0 Transaction with address only transfer type interrupt disabled.
1 Transaction with address only transfer type interrupt enabled.
Table 6-6. AIDR Field Descriptions (continued)
Bits Name Description