Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 6-7
6.2.5 Arbiter Interrupt Definition Register (AIDR)
The arbiter interrupt definition register (AIDR) determines the interrupt that responds to different error
conditions. Setting a bit defines the corresponding interrupt as MCP interrupt; clearing a bit defines the
corresponding interrupt as regular interrupt. Figure 6-5 shows the fields of AIDR.
Table 6-6 describes AIDR fields.
27 RES Reserved transfer type. Reports on transaction with reserved transfer type. See Section 6.3.2.5,
“Reserved Transaction Type,” for more information.
0 No transaction with reserved transfer type occurred.
1 Transaction with reserved transfer type occurred.
28 ECW External control word transfer type. Reports on transaction with external control word transfer type. See
Section 6.3.2.6, “Illegal (eciwx/ecowx) Transaction Type,” for more information.
0 No transaction with external control word transfer type occurred.
1 Transaction with external control word transfer type occurred.
29 AO Address Only transfer type. Reports on transaction with address only transfer type. See Section 6.3.2.4,
“Address Only Transaction Type,” for more information.
0 No transaction with address only transfer type occurred.
1 Transaction with address only transfer type occurred.
30 DTO Data time out. Reports on data tenure time out.
0 Data time out timer is not expired.
1 Data time out timer is expired.
31 ATO Address time out. Reports on address tenure time out.
0 Address time out timer is not expired.
1 Address time out timer is expired.
Offset 0x10 Access: User read/write
0 25 26 27 28 29 30 31
R
— ETEA RES ECW AO DTO ATO
W
Reset All zeros
Figure 6-5. Arbiter Interrupt Definition Register (AIDR)
Table 6-6. AIDR Field Descriptions
Bits Name Description
0–25 — Write reserved, read = 0
26 ETEA Transfer error. Detection of transfer error by one of the slaves interrupt definition.
0 Detection of transfer error by one of the slaves causes regular interrupt.
1 Detection of transfer error by one of the slaves causes MCP interrupt.
27 RES Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes regular interrupt.
1 Transaction with reserved transfer type causes MCP interrupt.
Table 6-5. AER Field Descriptions (continued)
Bits Name Description