Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
6-4 Freescale Semiconductor
6.2.2 Arbiter Timers Register (ATR)
The arbiter timers register (ATR) defines the arbiter address time out (ATO) and data time out (DTO)
values. Figure 6-2 shows the fields of ATR.
21–23 RPTCNT Repeat count. Specifies the maximum number of consecutive transactions, that any master can
perform, using REPEAT
request mode.
000 1 consecutive transactions (REPEAT
request mode disable)
001 2 consecutive transactions
010 3 consecutive transactions
011 4 consecutive transactions
100 5 consecutive transactions
101 6 consecutive transactions
110 7 consecutive transactions
111 8 consecutive transactions
Note: It is recommended not to program this field for more than four consecutive transactions.
24–25 — Write reserved, read = 0
26–27 APARK Address parking. Specifies arbiter bus parking mode.
00 Park to master. Arbiter parks the address bus to the master, that is selected by numeric value of
PARKM field.
01 Park to last owner. Arbiter parks the address bus to last bus owner.
10 Disable. Arbiter does not assert BG
to any master, if no BR is present.
11 Reserved
28–31 PARKM Parking master.
0000 e300 core
0001 Reserved
0010 TSEC1, TSEC2
0011 Reserved
0100 DMA, eSDHC, USB
0101 PCI Express
0110–1111 Reserved
Offset 0x04 Access: User read/write
0151631
R
DTO ATO
W
Reset11111111111111111111111111111111
Figure 6-2. Arbiter Timers Register (ATR)
Table 6-2. ACR Field Descriptions (continued)
Bits Name Description