Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 6-3
6.2.1 Arbiter Configuration Register (ACR)
The arbiter configuration register (ACR) defines the arbiter modes and parked master on the bus.
Figure 6-1 shows the fields of ACR.
Table 6-2 describes ACR fields.
Offset 0x00 Access: User read/write
0 6 7 8 9 10111213 15
R
— COREDIS — — PIPE_DEP
W
Reset All zeros
1
16 20 21 23 24 25 26 27 28 31
R
— RPTCNT — APARK PARKM
W
Reset All zeros
1
1
Note that the reset value of COREDIS and bits 10–11 are determined from reset configuration word. (See
Section 4.3.2, “Reset Configuration Words,” for more details on reset configuration word.)
Figure 6-1. Arbiter Configuration Register (ACR)
Table 6-2. ACR Field Descriptions
Bits Name Description
0–6 — Write reserved, read = 0
7 COREDIS Core disable. Specifies whether CPU is disabled. When CPU is disabled, it cannot be granted on the
bus by the arbiter. After reset, this bit receives its value from the reset configuration bit of COREDIS
and can be configured by software. Also, if boot source is boot sequencer, COREDIS must be set to
1 at reset and the last transaction of the boot sequencer must set COREDIS to 0, if CPU enable is
needed.
0 CPU enabled.
1 CPU disabled.
8–9 — Write reserved, read = 0
10–11 — Reserved. Write should preserve reset value. The reset value is a function of the core PLL
configuration, which is part of the reset configuration word. When the core is set to operate at 1:1 or
3:2 bus clock, these bits are set to ‘01’ during reset; otherwise, they are set to ‘00’.
12 — Write reserved, read = 0
13–15 PIPE_DEP Pipeline depth (number of outstanding transactions).
000 Pipeline depth 1 (1 outstanding transaction)
001 Pipeline depth 2 (2 outstanding transactions)
010 Pipeline depth 3 (3 outstanding transactions)
011 Pipeline depth 4 (4 outstanding transactions)
1xx Reserved
16–20 — Write reserved, read = 0