Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
6-2 Freescale Semiconductor
consecutive transactions can be limited by programming arbiter configuration register. See Section 6.2.1,
“Arbiter Configuration Register (ACR),” for more details.
NOTE
Write accesses to different interfaces are not guaranteed to finish in order.
6.2 Arbiter Memory Map/Register Definition
Table 6-1 shows the memory map for arbiter’s configuration, control, and status registers.
Table 6-1. Arbiter Register Map
System Arbiter—Block Base Address 0x0_0800
Memory
Offset (Hex)
Register Access Reset Section/Page
0x00 Arbiter configuration register (ACR) R/W 0x0000_0000/
0x0010_0000
1
1
Reset value is determined from the core PLL configuration of the reset configuration word. See Chapter 4, “Reset, Clocking,
and Initialization,” for details.
6.2.1/6-3
0x04 Arbiter timers register (ATR) R/W FFFF_FFFF 6.2.2/6-4
0x08 Arbiter Event Enable Register (AEER) R/W 0x0000_003F 6.2.3/6-5
0x0C Arbiter event register (AER) w1c 0x0000_0000 6.2.4/6-6
0x10 Arbiter interrupt definition register (AIDR) R/W 0x0000_0000 6.2.5/6-7
0x14 Arbiter mask register (AMR) R/W 0x0000_0000 6.2.6/6-8
0x18 Arbiter event attributes register (AEATR) R 0x0000_0000
2
2
The registers AEATR and AEADR are affected only by the assertion of PORESET.
6.2.7/6-9
0x1C Arbiter event address register (AEADR) R 0x0000_0000
2
6.2.8/6-10
0x20 Arbiter event response register (AERR) R/W 0x0000_0000 6.2.9/6-11