Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-72 Freescale Semiconductor
5.7.3.1 Shutting Down Clocks to Unused Blocks
As described in Section 4.5.2.3, “System Clock Control Register (SCCR),” SCCR provides a way to shut
down certain functional blocks within the device when they are not needed in a particular system. SCCR
can be written by the e300 core or by an external master. Powering down a block in this way turns off all
clocks to that block. It does not remove power. It is required that the SCCR is written to shut down a certain
functional block only when that block is idle.
NOTE
Functional blocks disabled using SCCR cannot respond to configuration
accesses. Any access to configuration, control, and status registers of a
disabled block is a programming error.
5.7.3.2 Software-Controlled Power-Down States
e300 core software can place the core in doze, nap, or sleep power-down states by writing to HID0 in the
core, as described in detail in the section “Hardware Implementation Register 0 (HID0),” of the e300
PowerPC Core Reference Manual. In addition, if PMCCR[SLPEN] is set when the e300 core request to
enter nap or sleep modes, it also causes the DDR2 controller to enter low-power mode. The basic
relationships between core and system power management states is shown in Table 5-67.
To preserve cache coherency and otherwise avoid loss of system state, the core transitions to low-power
modes is coordinated with DDR2 controller. The power management controller allows the core to enter
power-down mode only when the rest of the system is idle.
When the power management controller detects that the internal system bus is idle, and there are no
outstanding transactions, it signals the internal logic units to enter low-power state.
If PMCCR[DLPEN] and/or PMCCR[SLPEN] is set, the DDR SDRAM is first set to self-refresh mode (if
enabled by DDR_SDRAM_CFG[SREN] memory controller register) before the memory controller stops
driving refresh commands. Self-refresh mode guarantees that the memory content remains valid while the
memory controller and its clocks are off. The DDR clocks are then disabled. The DLL is then shut off and
stops driving clocks on MCKn pins. Finally the DDR SDRAM memory controller enters low-power state
and acknowledges the power management controller.
The power management controller then signals the core and acknowledges its request to enter power-down
mode. Finally the QUIESCE output signal is asserted.
Low Power
(PMCCR[SLPEN]
=1)
Nap Core operation as described above. System is
in idle state, DDR SDRAM memory operates in
self-refresh mode if enabled.
No Yes
According
to PMCCR
[DLPEN]
Asserted
Sleep
Table 5-67. Software-Controller Power-Down States—Basic Description (continued)
System Mode
Core
Mode
Description
Core Responds To DDR
SDRAM
State
Quiesce
Signal
StateSnoop Interrupt