Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-71
Table 5-66 defines the bit fields of PMCCR.
‘
5.7.3 Functional Description
The device has features to minimize power consumption at several levels. Software can shut down clocks
to individual blocks when they are not needed through a memory-mapped register in the clock unit
(SCCR). Additionally, software running on the e300 core can access the e300 core’s SPRs to put the e300
core into doze, nap, or sleep power-down states. These power management features are described in
further detail in this section.
There are four power states in MPC8308:
• D0: Full-power state
• D1: Core in doze mode, e300 PLL running
• D2: Core in nap mode, e300 PLL running
• D3: Core in sleep mode, e300 PLL not running
Table 5-66. PMCCR Bit Settings
Bits Name Description
0–29 — Reserved. Write has no effect, read returns 0.
30 DLPEN DDR SDRAM low power enable
0 The DDR SDRAM memory controller is prevented from entering low-power state.
1 The DDR SDRAM memory controller enters low-power state when the rest of the system enters
low-power, according to SLPEN setting. DDR SDRAM enters self-refresh mode (if enabled by
DDR_SDRAM_CFG[SREN] memory controller register) and DDR clocks (MCKn) are shut off. This bit is
cleared when the device exits from low-power state. Note that setting this bit without setting SLPEN has
no effect.
31 SLPEN System low power enable
0 The system is prevented from entering low-power state.
1 The system enters low-power state when a quiesce signal is generated from e300 core. This bit is
cleared when the device exits from low-power state.
Table 5-67. Software-Controller Power-Down States—Basic Description
System Mode
Core
Mode
Description
Core Responds To DDR
SDRAM
State
Quiesce
Signal
StateSnoop Interrupt
Full On
(PMCCR[SLPEN]
=0)
Full On The e300 core is operating normally Yes Yes Active Negated
Doze Core stops dispatching new instructions (core
is halted), and most of the core functional units
are disabled. System operates normally.
Yes Yes Active Negated
Nap Core is stopped with its clocks off except to
time base. System operates normally.
No Yes Active Negated
Sleep Core is stopped with its clocks off. Core clocks
to all blocks (including core time base) are
stopped except to the interrupt unit. System
operates normally.