Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-70 Freescale Semiconductor
5.7.1 External Signal Description
Table 5-64 describes the power management signals.
5.7.2 PMC Memory Map/Register Definition
Table 5-65 shows the memory map for the power management controller registers.
5.7.2.1 Power Management Controller Configuration Register (PMCCR)
The power management controller configuration register (PMCCR), shown in Figure 5-54, controls
whether only the e300 core enters low-power state upon quiesce request or additional parts of the device
also enters low-power state.
Figure 5-54. Power Management Controller Configuration Register
Table 5-64. System Control Signals—Detailed Signal Descriptions
Signal I/O Description
QUIESCE O Quiesce state. Indicates that the processor system and e300 core are in low- power state.
State
Meaning
Asserted—The system and e300 core are in low-power state.
Negated—The system and e300 core are not in low-power state.
Timing The timing between a quiesce request from the e300 core and the assertion of the external
indication or between negation of the e300 core’s quiesce request and negation of the external
indication depends on the current state of the internal system units and may vary accordingly.
Table 5-65. Power Management Controller Registers Memory Map
Offset Register Access Reset Section/Page
PMC—Block Base Address 0x0_0B00
0x00B00 Power management controller configuration register (PMCCR) R/W 0x0000_0000 5.7.2.1/5-70
0x00B04–
0x00BFC
Reserved — — —
Offset 0x00B00 Access: Read/Write
0 29 30 31
R
— DLPEN SLPEN
W
Reset All zeros