Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-68 Freescale Semiconductor
In this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter: timer 1 may be
internally cascaded to timer 2 and timer 3 may be internally cascaded to timer 4, as shown in
Figure 5-52. Since the decision to cascade timers is made independently, the user has the option of
selecting two 16-bit timers and one 32-bit timer (GTCFR1[PCAS] = 1, GTCFR2[PCAS] = 0 or
GTCFR1[PCAS1] = 0, GTCFR2[PCAS] = 1), or two 32-bit timers (GTCFR1[PCAS] = 1 and
GTCFR2[PCAS] = 1).
If GTCFR1[PCAS] = 1 and/or GTCFR2[SCAS] = 1, the two 16-bit timers (timer 1 and timer 2 or
timer 3 and timer 4) function as a 32-bit timer with a 32-bit GTRFR, GTCPR, and GTCNR. In this
case, GTMDR1/GTMDR3 is ignored, and the modes and functions are defined using
GTMDR2/GTMDR4 and GTCFR1/GTCFR2. The capture are controlled from TIN2, and the
interrupts are generated from GTEVR2. When working in the pair-cascaded mode, the cascaded
GTRFR, GTCPR, and GTCNR should be referenced with 32-bit bus cycles.
Figure 5-52. Timer Pair-Cascaded Mode Block Diagram
• Super-cascaded mode (GTCFR2[SCAS] = 1)
In this mode, all four 16-bit timers can be internally cascaded to form a 64-bit counter, as shown
in Figure 5-53.
If GTCFR2[SCAS] = 1, the all four 16-bit timers function as a 64-bit timer with a cascaded 32-bit
GTRFR, GTCPR, and GTCNR. In this case, registers GTMDR1, GTMDR2, GTMDR3, and
GTCFR1 are ignored, and the modes and functions are defined using GTMDR4 and GTCFR2 only.
The capture are controlled from TIN4, and the interrupts are generated from GTEVR4. When
working in the super-cascaded mode, the cascaded GTRFR, GTCPR, and GTCNR should be
referenced with two 32-bit bus cycles.
Figure 5-53. Timers Super-Cascaded Mode Block Diagram
Timer1
Timer2
Capture
Clock
GTRFR1, GTCPR1, GTCNR1
connected to D[31–16]
GTRFR2, GTCPR2, GTCNR2
connected to D[15–0]
Timer3
Timer4
Capture
Clock
GTRFR3, GTCPR3, GTCNR3
connected to D[31–16]
GTRFR4, GTCPR4, GTCNR4
connected to D[15–0]
Timer1
Timer2
Capture
GTRFR1, GTCPR1, GTCNR1
connected to D[63–48]
GTRFR2, GTCPR2, GTCNR2
connected to D[47–32]
Timer3
Timer4
Clock
GTRFR3, GTCPR3, GTCNR3
connected to D[31–16]
GTRFR4, GTCPR4, GTCNR4
connected to D[15–0]