Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-65
Table 5-62 defines the bit fields of GTEVRn.
5.6.5.7 Global Timers Prescale Registers (GTPSR1–GTPSR4)
The global timers prescale registers (GTPSR1, GTPSR2, GTPSR3, and GTPSR4) are shown in
Figure 5-50.
Erratic behavior may occur if GTPSRn is not initialized before the corresponding GTMDRn.
Table 5-63 defines the bit fields of GTPSRn.
NOTE
The total timer prescale value is calculated as follows:
This gives a total prescale range from 1 (GTPSRn[PPS] = 0x00,
GTMDRn[SPS] = 0x00) to 65,536 (GTPSRn[PPS] = 0xFF,
GTMDR[SPS] = 0xFF).
Table 5-62. GTEVRn Bit Settings
Bits Name Description
0–13 — Reserved, should be cleared.
14 REF Output reference event
0 No event
1 The counter reached the GTRFRn[TRV] value. GTMDRn[ORI] is used to enable the interrupt request
caused by this event.
15 CAP Counter capture event
Corresponding timer’s 16-bit read/write up-counter value.
0 No event
1 The counter value has been latched into the GTCPRn[LCV]. GTMDRn[CE] is used to enable generation
of this event.
Offset
0x38(GTPSR1)
0x3A(GTPSR2)
0x3C(GTPSR3)
0x3E(GTPSR4)
Access: Read/Write
07815
R
—PPS
W
Reset0000000000000011
Figure 5-50. Global Timers Prescale Registers (GTPSR1–GTPSR4)
Table 5-63. GTPSRn Bit Settings
Bits Name Description
0–7 — Reserved, should be cleared.
8–15 PPS Primary prescaler bits
The primary prescaler is programmed to divide the clock input to corresponding timer by values from 1 to 256.
The value 0x00 divides the clock by 1 and 0xFF divides the clock by 256.
GTMn
prescaler
GTPSRn PPS1+GTMDRn SPS1+=