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System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-64 Freescale Semiconductor
Table 5-60 defines the bit fields of GTCPRn.
5.6.5.5 Global Timers Counter Registers (GTCNR1–GTCNR4)
Global timers counter registers (GTCNR1, GTCNR2, GTCNR3, and GTCNR4), shown in Figure 5-48, are
four 16-bit, memory-mapped, read/write up-counters. A read cycle to a GTCNRn[CNV] fields yields the
current value of the appropriate timer but does not affect the counting operation. A write cycle to a
GTCNRn[CNV] field sets the register to the written value, causing its corresponding primary and
secondary prescaler counters to be reset.
Table 5-61 defines the bit fields of GTCNR.
5.6.5.6 Global Timers Event Registers (GTEVR1–GTEVR4)
Global timers event registers (GTEVR1, GTEVR2, GTEVR3, and GTEVR4), shown in Figure 5-49, are
used to report events recognized by any of the timers. On recognition of an output reference event, the
appropriate timer sets GTEVRn[REF], regardless of the corresponding GTMDRn[ORI]. The capture event
is only set if it is enabled by GTMDRn[CE]. GTEVRs appear as memory-mapped registers to users, which
can be read at any time.
GTEVRn bits are cleared by writing ones to them (writing zeros does not affect bit values). Both bits must
be reset before the timer negates the interrupt to the interrupt controller.
Table 5-60. GTCPRn Bit Settings
Bits Name Description
0–15 LCV Latched counter value. Corresponding timer’s 16-bit latched value.
Offset
0x1C(GTCNR1)
0x1E(GTCNR2)
0x2C(GTCNR3)
0x2E(GTCNR4)
Access: Read/Write
0 15
R
CNV
W
Reset All zeros
Figure 5-48. Global Timers Counter Registers (GTCNR1—GTCNR4)
Table 5-61. GTCNR Bit Settings
Bits Name Description
0–15 CNV Counter value.
Corresponding timer’s 16-bit read/write up-counter value.
Offset 0x30(GTEVR1)
0x32(GTEVR2)
0x34(GTEVR3)
0x36(GTEVR4)
Access: w1c
0 13 14 15
R
—
REF CAP
W w1c w1c
Reset All zeros
Figure 5-49. Global Timers Event Registers (GTEVR1—GTEVR4)