Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xx Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
5-18 PCI Express Controller Registers (PECR1).......................................................................... 5-29
5-19 eSDHC Control Register (SDHCCR)................................................................................... 5-30
5-20 RTC Control Register (RTCCR)........................................................................................... 5-32
5-21 Software Watchdog Timer High-Level Block Diagram ....................................................... 5-33
5-22 System Watchdog Control Register (SWCRR)..................................................................... 5-34
5-23 System Watchdog Count Register (SWCNR)....................................................................... 5-35
5-24 System Watchdog Service Register (SWSRR) ..................................................................... 5-36
5-25 Software Watchdog Timer Service State Diagram................................................................ 5-37
5-26 Software Watchdog Timer Functional Block Diagram......................................................... 5-38
5-27 RTC Block Diagram.............................................................................................................. 5-40
5-28 Real Time Counter Control Register (RTCNR).................................................................... 5-42
5-29 Real Time Counter Load Register (RTLDR) ........................................................................ 5-43
5-30 Real Time Counter Prescale Register (RTPSR).................................................................... 5-43
5-31 Real Time Counter Register (RTCTR).................................................................................. 5-44
5-32 Real Time Counter Event Register (RTEVR)....................................................................... 5-44
5-33 Real Time Counter Alarm Register (RTALR) ...................................................................... 5-45
5-34 Real Time Clock Module Functional Block Diagram .......................................................... 5-46
5-35 Periodic Interval Timer High Level Block Diagram............................................................. 5-48
5-36 Periodic Interval Timer Control Register (PTCNR) ............................................................. 5-49
5-37 Periodic Interval Timer Load Register (PTLDR).................................................................. 5-50
5-38 Periodic Interval Timer Prescale Register (PTPSR) ............................................................. 5-50
5-39 Periodic Interval Timer Counter Register (PTCTR) ............................................................. 5-51
5-40 Periodic Interval Timer Event Register (PTEVR)................................................................. 5-51
5-41 Periodic Interval Timer Functional Block Diagram.............................................................. 5-52
5-42 Global Timers Block Diagram.............................................................................................. 5-54
5-43 Global Timers Configuration Register 1 (GTCFR1)............................................................. 5-59
5-44 Global Timers Configuration Register 2 (GTCFR2)............................................................. 5-60
5-45 Global Timers Mode Registers (GTMDR1–GTMDR4)........................................................ 5-62
5-46 Global Timers Reference Registers (GTRFR1–GTRFR4).................................................... 5-63
5-47 Global Timers Capture Registers (GTCPR1–GTCPR4) ....................................................... 5-63
5-48 Global Timers Counter Registers (GTCNR1—GTCNR4).................................................... 5-64
5-49 Global Timers Event Registers (GTEVR1—GTEVR4)........................................................ 5-64
5-50 Global Timers Prescale Registers (GTPSR1–GTPSR4)........................................................ 5-65
5-51 Timers Non-Cascaded Mode Block Diagram....................................................................... 5-67
5-52 Timer Pair-Cascaded Mode Block Diagram......................................................................... 5-68
5-53 Timers Super-Cascaded Mode Block Diagram..................................................................... 5-68
5-54 Power Management Controller Configuration Register ....................................................... 5-70
6-1 Arbiter Configuration Register (ACR) ................................................................................... 6-3
6-2 Arbiter Timers Register (ATR) ............................................................................................... 6-4
6-3 Arbiter Event Enable Register (AEER) .................................................................................. 6-5
6-4 Arbiter Event Register (AER).................................................................................................6-6