Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-63
5.6.5.3 Global Timers Reference Registers (GTRFR1–GTRFR4)
Global timers reference registers, shown in Figure 5-46, are 16-bit memory-mapped, read/write registers
containing the 16-bit reference values for each timer’s timeout. The reference value is not reached until
GTCNRn[CNV] increments to the value in GTRFRn[TRV].
Table 5-59 defines the bit fields of GTRFR.
5.6.5.4 Global Timers Capture Registers (GTCPR1–GTCPR4)
Global timers capture registers (GTCPR1, GTCPR2, GTCPR3, and GTCPR4), shown in Figure 5-47, are
used to latch the value of the counters according to GTMDRn[CE].
13–14 ICLK Input clock source for the timer.
00 Internally cascaded input. This selection means: For ICLK1, the timer 1 input is the output of timer 2. For
ICLK2, the timer 1 input is the output of timer 2, the timer 2 input is the output of timer 3, the timer 3 input
is the output of timer 4. For ICLK3, the timer 3 input is the output of timer 4. For ICLK4 this selection means
no input clock is provided to the timer.
01 Internal general system bus clock.
10 Internal slow go clock (divided by 16 system bus clock).
11 TINn: corresponding TIN1, TIN2, TIN3, or TIN4 pin (falling edge).
15 GE Gate enable
0The TGATE
n signal is ignored.
1The TGATE
n signal is used to control the timer.
Offset
0x14(GTRFR1)
0x16(GTRFR2)
0x24(GTRFR3)
0x26(GTRFR4)
Access: Read/Write
0 15
R
TRV
W
Reset1111111111111111
Figure 5-46. Global Timers Reference Registers (GTRFR1–GTRFR4)
Table 5-59. GTRFR Bit Settings
Bits Name Description
0–15 TRV Timeout reference value.
16-bit timeout reference value for the corresponding timer. Set to all ones by reset.
Offset
0x18(GTCPR1)
0x1A(GTCPR2)
0x28(GTCPR3)
0x2A(GTCPR4)
Access: Read only
0 15
R LCV
W
Reset All zeros
Figure 5-47. Global Timers Capture Registers (GTCPR1–GTCPR4)
Table 5-58. GTMDR Bit Settings (continued)
Bits Name Description