Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-61
Table 5-57 defines the bit fields of GTCFR2.
Table 5-57. GTCFR2 Bit Settings
Bits Name Description
0 PCAS Pair-cascade mode
0 Normal operation.
1 Timers 3 and 4 cascade to form a 32-bit timer.
Note: This bit is ignored in super-cascade mode (GTCFR2[SCAS] = 1).
Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
Thus, the user should first clear the RST3 and RST4 bits (without changing PCAS) and then, in a
separate write to the register, change the value of PCAS.
1 SCAS Super cascade mode
0 Normal operation
1 Timers 1, 2, 3 and 4 cascade to form a 64-bit timer.
Note: In super-cascade mode (GTCFR2[SCAS] = 1) the pair-cascade mode bits are ignored,
(GTCFR1/2[PCAS] = Don’t Care).
Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
Thus, the user should first clear the RST1, RST2, RST3, and RST4 bits (without changing SCAS)
and then, in a separate write to the register, change the value of SCAS.
2 STP4 Stop timer 4
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 4, except the
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
3 RST4 Reset timer 4
0 Reset the timer 4, including GTMDR4, GTRFR4, GTCNR4, GTCPR4, and GTEVR4 (a software reset is
identical to an external reset).
1 Enable the corresponding timer if the STP4 bit is cleared.
4 GM4 Gate mode for TGATE4
0 Restart gate mode. The TGATE4 is used to enable/disable count. A low level of TGATE4 enables and a
falling edge of TGATE4 restarts the count (reset the dynamic counter’s count value to 0) and a high level
of TGATE4 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE4
does not restart the
appropriate count value in GTCNR4[CNV4].
5 GM3 Gate mode for TGATE3
0 Restart gate mode. The TGATE3 is used to enable/disable count. A low level of TGATE3 enables and a
falling edge of TGATE3
restarts the count (reset the dynamic counter’s count value to 0) and a high level
of TGATE3 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE3 does not restart the
appropriate count value in GTCNR3[CNV3].
Note: In backward-compatible mode (GTCFR1[BCM] = 0) this bit is ignored. The GTCFR2[GM4] bit
controls the gate mode for timers 3 and 4.
6 STP3 Stop timer 3
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 3, except the
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
7 RST3 Reset timer 3
0 Reset the timer 3, including GTMDR3, GTRFR3, GTCNR3, GTCPR3, and GTEVR3 (a software reset is
identical to an external reset).
1 Enable the corresponding timer if the STP3 bit is cleared.