Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-60 Freescale Semiconductor
The GTCFR2 register is shown in Figure 5-44.
5 GM1 Gate mode for TGATE1
0 Restart gate mode. The TGATE1 is used to enable/disable count. A low level of TGATE1 enables and a
falling edge of TGATE1 restarts the count (reset the dynamic counter’s count value to 0) and a high level
of TGATE1
disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1
does not restart the
appropriate count value in GTCNR1[CNV1].
Note: In backward-compatible mode (GTCFR1[BCM] = 0) this bit is ignored. GTCFR1[GM2] bit controls the
gate mode for timers 1 and 2.
6 STP1 Stop timer 1
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 1, except the
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
7 RST1 Reset timer 1
0 Reset the timer 1, including GTMDR1, GTRFR1, GTCNR1, GTCPR1, and GTEVR1 (a software reset is
identical to an external reset).
1 Enable the corresponding timer if the STP1 bit is cleared.
Offset
0x04 Access: Read/Write
01234567
R
PCAS SCAS STP4 RST4 GM4 GM3 STP3 RST3
W
Reset All zeros
Figure 5-44. Global Timers Configuration Register 2 (GTCFR2)
Table 5-56. GTCFR1 Bit Settings (continued)
Bits Name Description