Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-59
and resetting of a pair of timers (1 and 2 or 3 and 4) or of a groups of timers (1, 2, 3, and 4) if one bus cycle
is used. GTCFR is cleared by reset.
NOTE
For proper operation of the timers, do not change the modes of operation and
enable the timer in the same register write operation. The modes can be
changed when GTCFRn[RSTn] is cleared. However, when GTCFRn[RSTn]
are set, they are the only bits that can be changed.
Table 5-56 defines the bit fields of GTCFR1.
Offset
0x00 Access: Read/Write
01234567
R
PCAS BCM STP2 RST2 GM2 GM1 STP1 RST1
W
Reset All zeros
Figure 5-43. Global Timers Configuration Register 1 (GTCFR1)
Table 5-56. GTCFR1 Bit Settings
Bits Name Description
0 PCAS Pair-cascade mode
0 Normal operation
1 Timers 1 and 2 cascade to form a 32-bit timer.
Note: This bit is ignored in super-cascade mode (GTCFR2[SCAS] = 1).
Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
Thus, the user should first clear the RST1 and RST2 bits (without changing PCAS) and then, in a
separate write to the register, change the value of PCAS.
1 BCM Backward-compatible mode
0 Provide backward compatibility to PowerQUICC II family timers. In this mode GTCFR1[GM2] bit controls
the gate mode for timers 1 and 2 and GTCFR2[GM4] bit controls the gate mode for timers 3 and 4.
GTCFR1[GM1] and GTCFR2[GM3] bits are ignored.
1 Normal operational mode
2 STP2 Stop timer 2
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 2, except the
Register Interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
3 RST2 Reset timer 2
0 Reset the timer 2, including GTMDR2, GTRFR2, GTCNR2, GTCPR2, and GTEVR2 (a software reset is
identical to an external reset).
1 Enable the corresponding timer if the STP2 bit is cleared.
4 GM2 Gate mode for TGATE2
0 Restart gate mode. The TGATE2 pin is used to enable/disable count. A low level of TGATE2 enables and
a falling edge of TGATE2
restarts the count (reset the dynamic counter’s count value to 0) and a high
level of TGATE2
disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2
does not restart the
appropriate count value in GTCNR2[CNV2].