Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-57
Table 5-54 provides detailed descriptions of the external GTM signals.
5.6.5 GTM Memory Map/Register Definition
The GTM programmable register map occupies 64 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All GTM registers are 8 or 16 bits wide, located on 8-bit or 16-bit address boundaries, and should only be
accessed as 8-bit or 16-bit quantities. All addresses used in this chapter are offsets from GTM, as defined
in Chapter 3, “Memory Map.”
Table 5-54. GTM External Signals—Detailed Signal Descriptions
Signal I/O Description
TINn I Global timer capture control signal. Used to latch the value of the counter when a defined transition of
TINn is sensed by the corresponding input capture edge detector.
State
Meaning
Asserted/Negated —According to the programmed polarity by the corresponding
GTMDRn[CE]). Each timer has a 16-bit GTCPR used to latch the value of the counter
when a defined transition of TINn is sensed by the corresponding input capture edge
detector. Upon a capture or reference event, the corresponding GTEVR bit is set and
a maskable interrupt request is issued to the interrupt controller.
Timing Assertion/Negation—Asynchronous to internal bus clock. TINn is internally synchronized to
the system bus clock. If TINn meets the asynchronous input setup time, the value of
counter is captured after one system bus clock when working with the internal clock.
TGATE
n I Global timer counter gate control signal. Used to gate/restart the counter when a defined transition of
TGATE
n is sensed by the corresponding input capture edge detector.
State
Meaning
Asserted/Negated—According to the programmed polarity by the corresponding
GTCFR[GMx] bits. In a restart gate mode (GTCFR[GMn] = 0), the TGATEn pin is used
to enable/disable count. A falling TGATEn pin enables and restarts the count and a
rising edge of TGATE
n disables the count. In a normal gate mode (GTCFR[GMn] = 1),
the TGATEn have similar functionality, except the falling edge of TGATEn does not
restart the appropriate count value in GTCNRn[CNVn].
Timing Assertion/Negation—Asynchronous to internal bus clock. TGATEn is internally
synchronized to the system bus clock. If TGATE
n meets the asynchronous input setup
time, the counter begins counting or stop counting depending on the signal state and
configured mode.
TOUTn O Global timer counter output signal. The GTM output a signal on the timer output pin TOUTn when the
reference value is reached.
State
Meaning
Asserted/Negated—According to the programmed polarity by the corresponding
GTMDRn[OMn].
1. Active-low pulse on TOUT
n for one timer input clock cycle as defined by the
GTMDRn[ICLKn] bits (GTMDRn[OMn] = 1). Thus, TOUT
n may be low for one general
system clock period, one general system slow go clock period, or one TINn pin clock
cycle period.
2. Toggle the TOUT
n pin (GTMDRn[OMn] = 0). TOUTn begins or stops counting, depending
on the signal state and the configured mode.
Timing Assertion/Negation—TOUTn changes occur on the rising edge of the timer input clock.