Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-54 Freescale Semiconductor
Figure 5-42 shows the functional GTM block diagram.
Figure 5-42. Global Timers Block Diagram
5.6.2 GTM Features
The key features of the timer include the following:
• The maximum input clock is the system bus clock
• Four 16-bit programmable timers
• Two timers cascaded internally or externally (using TIN and TOUT external signals) to form a
32-bit timer
• One timer cascaded internally or externally to form a 64-bit timer
• Maximum period of ~549.6 second (at 125-MHz bus clock and two prescalers each = 256 and slow
go mode = 4) for 16-bit timer
• Maximum period of ~8796 seconds (at 125-MHz bus clock and a prescaler = 256) for 32-bit timer
• Maximum period of thousands of years (at 125-MHz bus clock and prescaler = 256) for 64-bit
timer
• 8-nanosecond timer resolution (at 125-MHz bus clock and no prescaler)
• Resolution and maximum period can be traded off by selecting prescaler divisor
• Three programmable input clock sources for the timer prescalers
Event Register
Mode Register
16-Bit Counter
Capture Register
Reference Register
Divider
GTEVR1
GTMDR1
GTCNR1
GTRFR1
GTCPR1
General
TIN1
TOUT1
Timer1
Timer2
Global Configuration Register 1
TGATE1
GTCFR1
TIN2
TOUT2
System Clock
Prescale Register
GTPSR1
Registers Interface
clock
Timer
Clock
Generator
Capture
Detection
Synchronizer
Timer3
TOUT3
Timer4
TGATE3
TIN3
TIN4
TOUT4
TGATE2
TGATE4
GTCFR2